Cortex-A8 Technical Reference Manual - ARM Information Center

Expanded Note to include description of Monitor
mode access to non-secure banked copies of
registers
Revisions
c1, Secure Configuration Register on page 3-53 All revisions
Modified descriptions of events 0x45 and 0x46 Table 3-97 on page 3-85 All revisions
Added description for cache flow when both L1
and L2 are cacheable, write-back, write-allocate
Table 7-1 on page 7-5 All revisions
Table C-5 Differences between Issue J and Issue K
Change Location Affects
Updated description for CRm=c6 Opcode_2=1
cache and prefetch buffer maintenance operation
Revised description of how the Cortex-A8 uses
the CLK signal.
Updated description of the effect of a reset on the
NEON and VFP clocks.
Added NOTE to describe Debug behavior in
systems with no ROM Table.
Updated code for the code for transmit data
transfer.
Table 3-73 on page 3-69 All revisions
Clock domains on page 10-2 All revisions
NEON or ETM unit level gating on page 10-10 All revisions
• CP14 c0, Debug ROM Address Register on page 12-14
• DBGSELFADDR on page 12-66
All revisions
Example 12-4 on page 12-71 All revisions
Updated the code for polling the DCC. Example 12-6 on page 12-72 All revisions
Updated the sequence for reading a block of
words of memory.
Revised description of Floating-Point Status and
Control Register.
Revised description of Floating-Point Exception
Register.
Table C-4 Differences between Issue I and Issue J (continued)
Change Location Affects
Example 12-25 on page 12-83 All revisions
Floating-Point Status and Control Register, FPSCR on
page 13-12
All revisions
Floating-point Exception Register, FPEXC on page 13-14 All revisions
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