Cortex-A8 Technical Reference Manual - ARM Information Center

Instruction Cycle Timing
The Subnormal penalty column indicates whether additional cycles are required for subnormal
operands, subnormal intermediate values, or subnormal final results. This penalty only applies
when the VFP coprocessor has flush-to-zero mode disabled.
For operations that have the result penalty, six to seven additional cycles are required to format
the final result.
For operations that have the operand penalty:
• one subnormal operand requires five to six additional cycles
• two subnormal operands require nine to ten additional cycles
• three subnormal operands require nine to ten additional cycles plus an intermediate
penalty.
All 3-input operations FMAC, FNMAC, FMSC, or FNMSC are variations of multiply-add, that is, a
multiplication followed by an addition. The multiplication produces an intermediate result that
might itself be subnormal. This intermediate subnormal has a penalty that is the same as the
output penalty (applied to the multiply) plus the input penalty (applied to the addition), which
amounts to an additional 11-13 cycles.
A slightly simpler way to look at 3-input operation is to split them into equivalent multiply and
add instructions. A 3-input operation takes the same amount of time as its component
multiplication and addition, usually minus one cycle.
An FMAC operation with three normal operands might have a multiplication that takes 12
cycles and an addition that takes nine cycles. The corresponding multiply followed by add
instruction takes:
12 + 9 - 1 = 20 cycles
For a multiplication of a normal number with a subnormal number that results in a product that
is also subnormal, this operation has an operand and result penalty and takes a total of 21 to 25
cycles. We then add the subnormal product to another subnormal number, resulting in a normal
sum. This addition has two operand penalties, and takes a total of 18 to 20 cycles. The total time
the two operations take is between:
10 + 5 + 6 + 18 = 39 cycles and 12 + 6 + 7 + 20 = 45 cycles
The corresponding FMAC multiply followed by add instruction has two operand penalties of
nine to 10 cycles, an intermediate penalty of 11 to 13 cycles, and the cost of the multiply-add of
18 to 21 cycles. The total time is between:
9 + 11 + 18 = 38 cycles and 10 + 13 + 21 = 44 cycles
16.7.2 VFP instruction execution in the NFP pipeline
The NFP pipeline can execute a subset of the VFPv3 data-processing instructions more quickly
than the VFP coprocessor. The following constraints define which VFP instructions are
executable by the NFP pipeline:
• single-precision data-processing operations only
• RunFast mode must be enabled
• scalar only or non-short vector instructions
If these constraints are met, the following instructions can execute in the NFP pipeline:
• FADDS, FSUBS
• FABSS, FNEGS
• FMULS, FNMULS
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