Cortex-A8 Technical Reference Manual - ARM Information Center

LA Last Access
External Memory Interface
Table 9-8 AXI address channel for data transactions for load/store multiples
Transfer Alignment ENR FA LA ARADDR
[31:0]
Noncacheable,
or strongly
ordered, or
device LDMs
Noncacheable,
or strongly
ordered, or
device STMs
ARLEN
[2:0]
ARSIZE
[2:0]
ARBURST
[1:0]
ARLOCK
[1:0]
Even word Yes 1 0 [31:3]000 0 64-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
1 1 [31:3]000 0 64-bit Incr Normal
No 1 0 [31:3]000 0 64-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
1 1 [31:3]000 0 32-bit Incr Normal
Odd word Yes 1 0 [31:2]00 0 32-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 32-bit Incr Normal
No 1 0 [31:2]00 0 32-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
Even word Yes 1 0 [31:3]000 0 64-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
1 1 [31:3]000 0 64-bit Incr Normal
No 1 0 [31:3]000 0 64-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
1 1 [31:3]000 0 32-bit Incr Normal
Odd word Yes 1 0 [31:3]100 0 32-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 32-bit Incr Normal
No 1 0 [31:3]100 0 32-bit Incr Normal
0 0 [31:3]000 0 64-bit Incr Normal
0 1 [31:3]000 0 64-bit Incr Normal
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