Cortex-A8 Technical Reference Manual - ARM Information Center

alg_pass[3:0]
Design for Test
For the first failing array, read the alg_pass[3:0] field to identify the pass of the algorithm that
produced a failure. For example, the CKBD algorithm has four passes, wscan, rscan, wscan, and
rscan, numbered 1, 2, 3, and 4. Because failures only occur on reads, a CKBD failure results in
an alg_pass[3:0] value of b0010 or b0100.
pattern[5:0]
Read the pattern[5:0] field to identify the pattern running at the time of the first failure.
Table 11-2 on page 11-3 shows the pattern codes. This field is useful when running more than
one pattern during a GO-NOGO test.
L2 MBIST Datalog Register
Figure 11-6 shows the fields of the L2 MBIST Datalog Register.
failing_ram[4:0]
Figure 11-6 L2 MBIST Datalog Register bit assignments
Read the failing_ram[4:0] field to identify the RAMs that produce failures. The bits in this field
correspond to the bits in the L2_ram_sel[4:0] field in the L2 MBIST Instruction Register.
Table 11-6 on page 11-6 shows how each bit corresponds to one of the L2 RAMs. Testing more
than one RAM while not in bitmap test mode can set more than one failing_ram[4:0] bit to 1.
The least-significant bit that is set to 1 in the failing_ram[4:0] field indicates the first failing
RAM.
Note
When the L2ValSer bit is 0, the tag RAM and valid RAM are tested in parallel. When testing
both these RAM in parallel, a failure in either RAM sets both bit [3] and bit [4] in the
failing_ram[4:0] field to 1. To determine if the tag RAM, valid RAM, or both failed, process the
failing_bits[32:0] field, see Table 11-18 on page 11-13.
expect_data[3:0]
Read the expect_data[3:0] field for the expected data seed for the first failing RAM. Because
data seed toggling occurs throughout algorithm execution, the value in this field does not always
correspond to the programmed data seed.
fail_addr[16:0]
fail_addr[16:0]
expect_data[3:0]
failing_ram[4:0]
read_mux
failing_bits[32:0]
alg_pass[3:0]
pattern
[5:0]
Read the fail_addr[16:0] field for the physical address of the first RAM failure. This is the
address sent to the RAM through the L2 MBIST interface. See the Cortex-A8 Release Notes for
information on how you can construct this address.
When testing the data array, there are no cache way select bits, but the index value is still
right-justified with fail_addr[0]. You can ignore the upper bits of this field that might be unused
for smaller cache sizes (except for bit [16], which is always zero). The values shifted out of
unused address bits reflect the values assigned to those bits in the address scramble
configuration.
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