Cortex-A8 Technical Reference Manual - ARM Information Center

• the data after pass 1 of XADDRBAR using a data seed of 0.
YADDRBAR
Design for Test
Figure 11-22 XADDRBAR array accessing and data
The YADDRBAR pattern is similar to the XADDRBAR pattern with the exception of
incrementing and decrementing the array column-fast.
In a 4 4 array, Figure 11-23 shows:
• the order of array accesses during YADDRBAR execution
• the data after pass 1 of YADDRBAR using a data seed of 0.
WRITEBANG
Addressing
direction
Row
3
2
1
0
g o
e m
c k
a i
j b
l d
n f
p h
Col 0 1 2 3
Order of XADDRBAR
array accesses in
passes 1 and 2
Row
3
2
1
0
Addressing
direction
h f
p n
i k
a c
Figure 11-23 YADDRBAR array accessing and data
WRITEBANG is a row-fast bitline stress pattern. It operates on a bitline pair, that is, a column.
It tries to create slow reads from target data cells in the column that can cause hard faults in
self-timed and high-speed RAMs. It writes the bitline multiple times to the opposite data state
of the target read, trying to create an imbalance in the bitline pair that the cell must correct. The
pattern reveals insufficient bitline precharge or equalization. The target cell has opposite data
from all other cells on the bitline pair. This is a worst-case bitline condition for a cell to drive
because any leakage from other cells in the column oppose the targeted read. In the following
description, wsac indicates a write to row 0, a sacrificial (untested) row used during test.
WRITEBANG performs the following sequence:
1. Wscan data to entire array.
2. W_, R_, wsac, wsac, wsac, wsac, wsac, R_, W, incr.
3. Wscan databar.
4. W, R, wsac_, wsac_, wsac_, wsac_, wsac_, R, W_, incr.
Figure 11-24 on page 11-26 shows the state of row 1, column 2 in a 4 4 array during pass 2.
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d b
l j
m
o
e g
Col 0 1 2 3
Order of YADDRBAR
array accesses in
passes 1 and 2
Row
3
2
1
0
i a
k c
m e
o g
h p
f n
d l
b j
Col 0 1 2 3
Order of XADDRBAR
array accesses in
passes 3 and 4
Row
3
2
1
0
j l
b d
g e
o m
n p
f h
c a
k i
Col 0 1 2 3
Order of YADDRBAR
array accesses in
passes 3 and 4
Row
3
2
1
0
0 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
Col 0 1 2 3
XADDRBAR array
data after pass 1 with
data seed = 0
Row
3
2
1
0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
Col 0 1 2 3
YADDRBAR array
data after pass 1 with
data seed = 0