Cortex-A8 Technical Reference Manual - ARM Information Center

Bits Field
[19] Clock stop request
disable
[18] CP14/CP15 instruction
serialization
System Control Coprocessor
R R/W Disables CLKSTOPREQ:
0 = CLKSTOPREQ causes the processor to stop the internal
clocks and to assert the CLKSTOPACK output, reset value
1 = disables the CLKSTOPREQ functionality.
R R/W Some CP14 and CP15 instructions execute natively in a serial
manner. This control bit imposes serialization on those CP14
and CP15 instructions that are not natively serialized:
0 = does not enforce serialization of CP14 or CP15
instructions, reset value
1 = enforces serialization of CP14 and CP15 instructions.
[17] CP14/CP15 wait on idle R R/W Some CP14 or CP15 instructions that execute in a serial
manner require that all outstanding memory accesses
complete before execution of the instruction. This control bit
imposes wait on idle protocol of CP14 and CP15 serialized
instructions that do not natively wait on idle:
0 = does not enforce wait on idle of CP14 and CP15
instructions, reset value
1 = enforces wait on idle for serialized CP14 or CP15
instructions.
[16] CP14/CP15 pipeline
flush
R R/W After execution of some CP14 or CP15 instructions, the
processor natively performs a pipeline flush before it executes
the next instructions. This control bit imposes a pipeline flush
on CP14 and CP15 instructions that do not natively include
one:
0 = does not impose a pipeline flush on CP14 or CP15
instructions, reset value
1 = imposes a pipeline flush on CP14 and CP15 instructions.
[15] Force ETM clock R R/W Forces ETM clock enable active:
0 = does not prevent the processor clock generator from
stopping the ETM clock, reset value
1 = prevents the processor clock generator from stopping the
ETM clock.
[14] Force NEON clock R R/W Forces NEON clock enable active:
0 = does not prevent the processor clock generator from
stopping the NEON clock, reset value
1 = prevents the processor clock generator from stopping the
NEON clock.
[13] Force main clock R R/W Forces the main processor clock enable active:
0 = does not prevent the processor clock generator from
stopping the main clock, reset value
1 = prevents the processor clock generator from stopping the
main clock.
[12] Force NEON single
issue
Security State
NS S
Table 3-49 Auxiliary Control Register bit functions (continued)
Function
R R/W Forces single issue of Advanced SIMD instructions:
0 = does not force single issue of Advanced SIMD
instructions, reset value
1 = forces single issue of Advanced SIMD instructions.
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