Cortex-A8 Technical Reference Manual - ARM Information Center

Table 12-53 shows the values in the Link Register after exceptions. The ARM and Thumb
columns in this table represent the processor state in which the exception occurred.
12.7.1 Effect of debug exceptions on CP15 registers and WFAR
12.7.2 Avoiding unrecoverable states
The four CP15 registers that record abort information are:
• Data Fault Address Register (DFAR)
• Instruction Fault Address Register (IFAR)
• Instruction Fault Status Register (IFSR)
• Data Fault Status Register (DFSR).
See Chapter 3 System Control Coprocessor for more information on these registers.
If the processor takes a debug exception because of a watchpoint debug event, the processor
performs the following actions on these registers:
• it does not change the IFSR or IFAR
• it updates the DFSR with the debug event encoding
• it writes an Unpredictable value to the DFAR
Debug
Table 12-53 Values in Link Register after exceptions
Cause of fault ARM Thumb Return address (RA) meaning
Breakpoint RA+4 RA+4 Breakpointed instruction address
Watchpoint RA+8 RA+8 Address of the instruction that triggered the watchpoint event
BKPT instruction RA+4 RA+4 BKPT instruction address
Vector catch RA+4 RA+4 Vector address
Prefetch Abort RA+4 RA+4 Address of the instruction that the prefetch abort event canceled
Data Abort RA+8 RA+8 Address of the instruction that the data abort event canceled
• it updates the WFAR with the address of the instruction that accessed the watchpointed
address, plus a processor state dependent offset:
— + 8 for ARM state
— + 4 for Thumb and ThumbEE states.
If the processor takes a debug exception because of a breakpoint, BKPT, or vector catch debug
event, the processor performs the following actions on these registers:
• it updates the IFSR with the debug event encoding
• it writes an Unpredictable value to the IFAR
• it does not change the DFSR, DFAR, or WFAR.
The processor ignores vector catch debug events on the Prefetch or Data Abort vectors while in
Monitor debug-mode because these events put the processor in an unrecoverable state.
The debuggers must avoid other similar cases by following these rules, that apply only if the
processor is in Monitor debug-mode:
• if BCR[22:20] is set to b010, an unlinked context ID breakpoint is selected, then the
debugger must program BCR[2:1] for the same breakpoint as stated in this section
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