Cortex-A8 Technical Reference Manual - ARM Information Center

12.4.14 Breakpoint Control Registers
For an IVA and context ID pair, two BRPs must be linked. A debug event is generated when
both the IVA and the context ID pair match at the same time.
Table 12-22 shows how the bit values correspond with the Breakpoint Value Registers
functions.
Note
• Only BRP4 and BRP5 support context ID comparison.
Debug
• BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are Should-Be-Zero or Preserved on
writes and Read-As-Zero on reads because these registers do not support context ID
comparisons.
• The context ID value for a BVR to match with is given by the contents of the CP15
Context ID Register. See Chapter 3 System Control Coprocessor for information on the
Context ID Register.
The BCR is a read/write register that contains the necessary control bits for setting:
• breakpoints
• linked breakpoints.
Figure 12-12 shows the bit arrangement of the BCRs.
Table 12-22 Breakpoint Value Registers bit functions
Bits Field Description
[31:0] - Breakpoint value. The reset value is 0.
31 29 28 24 23 22 20 19 16 15 14 13 9 8 5 4 3 2 1 0
Breakpoint
address mask
Reserved
M Linked BRP Reserved
Byte
address
select
Reserved Secure state access control Reserved
Figure 12-12 Breakpoint Control Registers format
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