Cortex-A8 Technical Reference Manual - ARM Information Center

Level 2 Memory System
Note
It is entirely possible that the L1 data cache contains the same line that is transferred by the PLE
engine to the external memory. Therefore it is possible for the line to become valid in the L2
cache as a result of an L1 eviction.
During data transfers into the L2 cache RAM, any L2 cache RAM data present in a different L2
cache RAM way, other than the way specified by the L2 PLE Control Register bits [2:0], remain
in the different way. The preload engine continues with the next cache line to be loaded and the
line is not relocated to the specified way.
During transfers to or from the L2 cache RAM, if the PLE crosses a page boundary, a hardware
translation table walk is performed to obtain a new physical address for that new page. All
standard fault checks are also performed. If a fault occurs, the PLE signals an interrupt on error.
The PLE updates the L2 PLE Channel Status Register to capture the fault status. The address
where the fault occurred is captured in the L2 PLE Internal Start Address Register.
When a PLE channel completes the transfer of the data block to or from the L2 cache RAM, it
signals an interrupt. This interrupt can be either secure, nDMASIRQ, or nonsecure,
nDMAIRQ, if IC bit [29] in the L2 PLE Control Register is enabled. In addition, there might
be an interrupt-on-error, nDMAEXTERRIRQ, indicated if the PLE aborts for any reason and
if the interrupt-on-error bit is enabled.
If you program the PLE to load data into the L2 cache RAM, the PLE transfers data to the L2
cache RAM if the memory region type is cacheable. To determine the memory region type, the
PLE performs a hardware translation table walk at the start of the sequence and for any 4KB
page boundary. The PLE channel does not save any state for the table walk. The translation
procedure is for exception checking purposes and for determination of the memory attributes of
the page. Any unexpected L2 cache RAM hits found when using the PLE are ignored for any
type of data transfer.
Note
Both channels can run concurrently and be programmed to transfer data from external memory
to the same L2 cache RAM way. At the completion of both PLE transactions, the data from
either channel 0 or 1might be present in the L2 cache.
8.4.2 Preload engine commands and status interaction
When the preloading engine channel has been configured, the channel begins to transfer data
after it executes the start command. If at any time during the transfer, a preloading engine
channel command of stop or clear is executed, the following rules apply for that command:
START Channel status transitions from idle to running. It has no effect on a channel status
of running. The start and end address registers are updated as preloading engine
transfers complete.
STOP Channel status transitions from running to idle. The start and end address reflect
the next transfer to occur. When the channel is stopped, the address plus stride of
the last transfer is stored in the PLE Internal Start Address Register. In addition,
the remaining number of cache lines to be transferred is stored in the PLE Internal
End Address Register. Therefore, by executing a start command, the preloading
engine continues from the point when it was stopped.
CLEAR Channel status transitions from error or complete to idle and the interrupt or error
flag is cleared to 0. It has no effect on a channel status of running. The start and
end address registers are unchanged.
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