Cortex-A8 Technical Reference Manual - ARM Information Center

2.4 Jazelle Extension
2.4.1 Jazelle Identity Register
Programmers Model
The Cortex-A8 processor provides a trivial implementation of the Jazelle Extension. This means
that the processor does not accelerate the execution of any bytecodes, and all bytecodes are
executed by software routines.
In the implementation of the Jazelle Extension:
• Jazelle state is not supported
• The BXJ instruction behaves as a BX instruction.
See the ARM Architecture Reference Manual for information on Jazelle Extension.
The processor provides three registers for the implementation of the Jazelle Extension:
• the Jazelle Identity Register
• the Jazelle Main Configuration Register
• the Jazelle OS Control Register on page 2-8.
The Jazelle Identity Register enables software to determine the implementation of the Jazelle
Extension provided by the processor.
The Jazelle Identity Register is:
• in CP14 register c0
• a 32-bit read-only register, accessible in all processor modes and security states.
Figure 2-4 shows the bit arrangement of the Jazelle Identity Register.
Figure 2-4 Jazelle Identity Register format
Table 2-4 shows how the bit values correspond with the Jazelle Identity Register.
To access this register, read CP14 with:
2.4.2 Jazelle Main Configuration Register
31 0
Reserved
MRC p14, 7, , c0, c0, 0 ; Read Jazelle Identity Register
Table 2-4 Jazelle Identity Register bit functions
Bits Field Function
[31:0] - Read-As-Zero (RAZ)
The Jazelle Main Configuration Register controls features of the Jazelle Extension.
The Jazelle Main Configuration Register is:
• in CP14 register c0
• a 32-bit register, with access rights that depend on the current privilege:
— Write-only (WO) in User mode
— Read/Write (R/W) in Privileged modes.
Figure 2-5 on page 2-8 shows the bit arrangement of the Jazelle Main Configuration Register.
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