Cortex-A8 Technical Reference Manual - ARM Information Center

10.3 Power control
10.3.1 Dynamic power management
Clock, Reset, and Power Control
Both the clocks and resets in the processor play key roles in the power management of the
processor, enabling islands to be powered down or powered up in a controlled manner. They
also provide many key control mechanisms to manage dynamic power.
This section describes:
• Dynamic power management
• Static or leakage power management on page 10-11
• Debugging the processor while powered down on page 10-18
• L1 data and L2 cache power domains on page 10-19
• Special note on reset during power transition on page 10-22.
The processor has many different dynamic power management facilities. The most common
form of dynamic power management is control of the clock network within the processor.
The processor has three levels of clock gating to manage dynamic power. The levels correspond
to the following functions:
Level 1 This is architectural gating, also known as Wait-For-Interrupt (WFI), or the
CLKSTOPREQ and CLKSTOPACK signals on the Cortex-A8 processor.
Level 2 This is major function gating, such as NEON, ETM, or integer core gating.
Level 3 This is state element gating, such as local clock gating.
The processor contains all hardware necessary for architecture, unit, and local clock gating. No
external hardware is required to clock gate the processor.
Wait-For-Interrupt architecture
Executing a Wait-For-Interrupt instruction puts the processor into a low-power state until one
of the following occurs:
• an IRQ or FIQ interrupt
• a halting debug event when the DBGNOCLKSTOP signal is HIGH.
See Halting debug event on page 12-51 for information on halting debug events.
Note
• If you are debugging software running on the Cortex-A8 processor, DBGNOCLKSTOP
must be HIGH. Otherwise, halting debug events do not work as architected and the APB
interface does not return a response when accessing the ETM, CTI, or core domain debug
registers. See Table 12-3 on page 12-6 for information on the debug registers that are in
the core.
• If DBGNOCLKSTOP is HIGH and you execute the Wait-For-Interrupt instruction, the
processor goes into an idle state but not into a low-power state.
• The STANDBYWFI pin remains HIGH even when DBGNOCLKSTOP is HIGH.
When executing the WFI instruction, the processor waits for the following events to complete
before entering the idle or low-power state:
• L1 data memory system loads and stores are complete
• all L1 instruction memory system fetches are complete
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