Cortex-A8 Technical Reference Manual - ARM Information Center

EN b
Figure 3-42 shows the bit arrangement of the SWINCR Register.
System Control Coprocessor
Figure 3-42 Software Increment Register format
Table 3-90 shows how the bit values correspond with the SWINCR Register functions.
The SWINCR Register only has effect when counter event is set to 0x00.
Table 3-91 shows the results of attempted access for each mode.
To access the SWINCR Register, read or write CP15 with:
MRC p15, 0, , c9, c12, 4 ; Read SWINCR Register
MCR p15, 0, , c9, c12, 4 ; Write SWINCR Register
3.2.47 c9, Performance Counter Selection Register
31 4 3 2 1 0
Reserved
The purpose of the Performance Counter SELection (PMNXSEL) Register is to select a
Performance Monitor Count Register.
The PMNXSEL Register is:
• a read/write register common to Secure and Nonsecure states
• accessible as determined by c9, User Enable Register on page 3-89.
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P3
P2
P1
P0
Table 3-90 Software Increment Register bit functions
Bits Field Function
[31:4] - Reserved. RAZ, SBZP
[3] P3 Increment Counter 3
[2] P2 Increment Counter 2
[1] P1 Increment Counter 1
[0] P0 Increment Counter 0
Table 3-91 Results of access to the Software Increment Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 0 Data 0 Data Undefined Undefined Undefined Undefined
1 0 Data 0 Data 0 Data 0 Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. The EN bit in c9, User Enable Register on page 3-89 enables User mode access of the Performance Monitor Registers.