Cortex-A8 Technical Reference Manual - ARM Information Center

Debug
• The sequence can be abandoned and restarted from the beginning by writing the key again
to the OSLAR. However, the results of accesses issued before it was abandoned are
committed.
• If this register is read or written while the core is powered-down or the OS lock is not set,
the results are Unpredictable.
12.4.20 Device Power Down and Reset Control Register
The PRCR is a read/write register that controls reset and power-down related functionality.
Figure 12-17 shows the bit arrangement of the PRCR.
31 3 2 1 0
Figure 12-17 PRCR format
Table 12-30 shows how the bit values correspond with the Device Power Down and Reset
Control Register functions.
Bits Field Function
[31:3] - Reserved. RAZ, SBZP.
12.4.21 Device Power Down and Reset Status Register
Reserved
Hold internal reset
Reserved
No power down
Table 12-30 PRCR bit functions
[2] Hold internal reset Hold internal reset bit. This bit prevents the processor from running again before the
debugger detects a power-down event and restores the state of the debug registers in the
core power domain. This bit is also used to detect a reset (ARESETn) event. By
examining PRSR[1], the debugger can determine whether a power-down or a reset event
occurred. The effect of this bit is that if it is set to 1 and a processor reset occurs,
ARESETn or nPORESET, then the processor behaves as if ARESETn is still asserted,
until the debugger clears PRCR[2] to 0. This bit does not have any effect on initial system
power up as PRESETn clears it to 0:
0 = does not hold internal reset on power up or reset, reset value
1 = holds the processor nondebug logic in reset on power up or reset until this bit is cleared
to 0.
[1] - Reserved. RAZ, SBZP.
[0] No power down No power down. When set to 1, the DBGNOPWRDWN output signal is HIGH. This
output is connected to the system power controller and is interpreted as a request to operate
in emulate mode. In this mode, the core and ETM are not actually powered down when
requested by software or hardware handshakes. This mode is useful when debugging
applications on top of working operating systems:
0 = DBGNOPWRDWN is LOW, reset value
1 = DBGNOPWRDWN is HIGH.
The PRSR is a read-only register that provides information about the reset and power-down
state of the processor.
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