Cortex-A8 Technical Reference Manual - ARM Information Center

L1 inner policy a L2 outer policy
Noncacheable,
nonbufferable
Cacheable,
write-back, no
write-allocate
Cacheable,
write-back,
write-allocate
Cacheable,
write-back,
write-allocate
Cacheable,
write-through, no
write-allocate
Cacheable,
write-back, no
write-allocate
Cacheable,
write-back, no
write-allocate
Cacheable,
write-back, no
write-allocate
Cacheable,
write-through, no
write-allocate
Cacheable,
write-through, no
write-allocate
Cacheable,
write-through, no
write-allocate
Noncacheable,
bufferable
Cacheable,
write-through, no
write-allocate
Noncacheable,
nonbufferable
Noncacheable,
nonbufferable
Cacheable,
write-back,
write-allocate
Noncacheable,
nonbufferable
Cacheable,
write-back, no
write-allocate
Cacheable,
write-back,
write-allocate
Cacheable,
write-through, no
write-allocate
Cacheable,
write-back, no
write-allocate
Cacheable,
write-back,
write-allocate
Cacheable,
write-through, no
write-allocate
Noncacheable,
bufferable
a. You can configure the L2 cache to use the inner policy attributes.
Level 1 Memory System
Table 7-1 Memory types affecting L1 and L2 cache flows (continued)
Buffers
flushed Description
No Loads and stores are not cached at L1. Loads are not filled into
the fill buffer. Stores bypass integer store buffer and are
directly sent to L2. L2 store misses do not allocate the line into
L2 cache. Store hits are sent externally in addition to updating
L2.
No Load misses are filled into L1. Store misses are sent to L2. L2
does not allocate the line into L2 cache on an L2 miss but is
sent externally.
No This is not supported. L1 is always in the no write-allocate
mode.
No Load misses are allocated into L1. Store misses bypass integer
store buffer and are sent to L2. Store hits update the cache. L2
allocates the line into L2 cache for store misses.
No Load misses are filled into L1. Store hits and store misses are
sent to L2. L2 does not allocate the line into L2 cache on an L2
miss because it is sent externally.
No Load misses are allocated into L1. Store misses bypass integer
store buffer and are sent to L2. Store hits update the cache. L2
does not allocate the line into L2 cache on store misses.
No Load misses are allocated into L1. Store misses bypass integer
store buffer and are sent to L2. Store hits update the cache. L2
allocates the line into L2 cache for store misses.
No Load misses are allocated into L1. L2 makes store hits
write-through at L2 cache and does not allocate the line into
L2 for store misses.
No Loads are allocated into L1. Store hits are made write-through
at L1. Store hits update the cache and are sent to L2. L2 does
not allocate store misses but they are sent externally.
No Loads are allocated into L1. Store hits are made write-through
at L1. Store hits update the cache and are sent to L2. Store
misses are allocated into L2.
No Loads are allocated into L1. Store hits are made write-through
at L1. Store hits update the cache and are sent to L2. Store
misses are not allocated into L2.
No Loads are replayed and access is sent externally. Stores bypass
integer store buffer and are placed into L2 write buffer. Stores
are sent externally.
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