Cortex-A8 Technical Reference Manual - ARM Information Center

11.2 ATPG test features
11.2.1 Wrapper
processor
input ports
WEXTEST
WINTEST
WSE
This section describes test features that are included in the RTL to ensure that the DFT
implementation meets minimum requirements:
• Wrapper
• Enabling sections of the core on page 11-29
• Reset handling on page 11-30.
• Safe shift RAM signals on page 11-30.
Design for Test
There are seven input signals that control the logic of the core to support the Wrapper Boundary
Register (WBR) and the IEEE 1500 standard:
• WEXTEST
• WINTEST
• WSE
• CAPTUREWR
• TESTMODE
• SERIALTEST
• SHIFTWR.
This logic:
• separates the shift and capture for IEEE 1500 compliance so that the shared wrapper cell
can hold state when neither shifting nor capturing
• requires only one external wrapper scan enable and prevents unknown states in wrapper
cells with multiple capture cycles, which is preferable for delay testing and for testing
through the memories.
Figure 11-26 shows the RTL logic for a set of input WBR cells.
Single WSE logic
processor
input ports
CAPTUREWR
TESTMODE
SERIALTEST
SHIFTWR
Hold control logic
Figure 11-26 Input wrapper boundary register cell control logic
Figure 11-27 on page 11-29 shows the RTL logic for a set of output WBR cells.
capture_inputs_n
shift_inputs
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 11-28
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SEin
1
0
0
1
To input
WBR cells