Cortex-A8 Technical Reference Manual - ARM Information Center

2.15.10 Undefined instruction
Programmers Model
When the processor encounters an instruction that neither it nor any coprocessor in the system
can handle, it takes the Undefined Instruction exception. Software can use this mechanism to
extend the ARM instruction set by emulating Undefined coprocessor instructions.
After emulating the failed instruction, the exception handler executes the following instruction,
irrespective of the processor operating state:
MOVS PC,R14_und
2.15.11 Breakpoint instruction
2.15.12 Exception vectors
This action restores the CPSR and returns to the next instruction after the Undefined Instruction
exception.
IRQs are disabled when an Undefined Instruction exception occurs. See the ARM Architecture
Reference Manual for more information about Undefined instructions.
A breakpoint, BKPT, instruction operates as though the instruction causes a prefetch abort. A
breakpoint instruction does not cause the processor to take the prefetch abort exception until the
instruction reaches the Execute stage of the pipeline. If the processor does not execute the
instruction, for example because a branch occurs while it is in the pipeline, the breakpoint does
not take place.
After dealing with the breakpoint, the handler executes the following instruction irrespective of
the processor operating state:
SUBS PC,R14_abt,#4
This action restores both the PC and the CPSR, and retries the breakpointed instruction.
Note
If the EmbeddedICE-RT logic is configured into Halting debug-mode, a breakpoint instruction
causes the processor to enter debug state. See Halting debug-mode debugging on page 12-3.
The Secure Configuration Register bits [3:1] determine the mode that is entered when an IRQ,
a FIQ, or an external abort exception occurs. The CP15 c12, Secure or Nonsecure Vector Base
Address Register and the Monitor Vector Base Address Register define the base address of the
Nonsecure, Secure, and Secure Monitor vector tables. If high vectors are enabled using CP15
c1 bit[13], the base address of the Nonsecure and Secure vector tables is 0xFFFF0000, regardless
of the value of these registers. Enabling high vectors has no effect on the Secure Monitor vector
addresses.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 2-32
ID060510 Non-Confidential