Cortex-A8 Technical Reference Manual - ARM Information Center

9.4.3 NEON accesses to strongly ordered and device memory
9.4.4 AXI data address transactions
External Memory Interface
NEON vector type transfers are based on an element size and can require multiple AXI
transfers. Each transfer consists of incrementing burst transactions of up to 128-bit bus width
boundary. For example, if the Advanced SIMD instruction VLD1.16 {D0}, [r1] is executed to
address offset 0xE, then the following two burst transactions are generated on the AXI interface.
The first transaction consists of the following:
• ARBURST[1:0] = 0x1
• ARLEN[3:0] = 0x0 for single data transfer
• ARSIZE[2:0] = 0x1.
The second transaction consists of the following:
• ARBURST[1:0] = 0x1
• ARLEN[3:0] = 0x2 for three data transfers
• ARSIZE[2:0] = 0x1.
Table 9-7 shows the values of AxADDR[31:0], AxLEN[3:0], AxSIZE[2:0], AxBURST[1:0],
and AxLOCK[1:0] for data transactions excluding load/store multiples.
In this table:
NA Naturally Aligned
BW Bus Width
BC Boundary Cross
NoT Number of Transactions
TS Transaction sequence number if multiple transactions are required
SAO Starting Address Offset
AxA AxADDR, either ARADDR or AWADDR
AxLN AxLEN, either ARLEN or AWLEN
AxS AxSIZE, either ARSIZE or AWSIZE
AxB AxBURST, either ARBURST or AWBURST
AxLK AxLOCK, either ARLOCK or AWLOCK
Table 9-7 AXI address channel for data transactions - excluding load/store multiples
Transfer NA BW BC a NoT TS
MMU
translation table
walk b
Noncacheable,
or strongly
ordered, or
device load byte
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 9-7
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SAO
[3:0]
AxA
[31:0]
AxLN
[3:0]
AxS
[2:0]
AxB
[1:0]
AxLK
[1:0]
Yes 64 N/A 1 - - [31:2]00 0 32-bit Incr Normal
128 N/A 1 - - [31:2]00 0 32-bit Incr Normal
Yes 64 N/A 1 - - [31:0] 0 8-bit Incr Normal
128 N/A 1 - - [31:0] 0 8-bit Incr Normal