Cortex-A8 Technical Reference Manual - ARM Information Center

17.1 About setup and hold times
AC Characteristics
The setup and hold times of processor interface signals are necessary timing parameters for
analyzing processor performance. This chapter specifies the setup and hold times of the
processor interface signals.
The notation for setup and hold times of input signals is:
Tis Input setup time. Tis is the amount of time the input data is valid before the next
rising clock edge.
Tih Input hold time. Tih is the amount of time the input data is valid after the next
rising clock edge.
Figure 17-1 shows the setup and hold times of an input signal.
The time during which the processor can sample input data is Tissignal.
Figure 17-1 Input timing parameters
The notation for setup and hold times of output signals is:
Tov Output valid time. Tov is the amount of time after the rising clock edge before
valid output data appears.
Toh Output hold time. Toh is the amount of time the output data is valid after the next
rising clock edge.
Figure 17-2 shows the setup and hold times of an output signal.
Figure 17-2 Output timing parameters
The timing parameter tables in this chapter show setup and hold parameters of each signal as
percentages of the relevant clock as shown in Table 17-1.
The setup parameter values are based on the Slow-Slow (SS) corner under the following
conditions:
• 125 °C
• VDD = nominal operating voltage – 10%
• target frequency = fmax.
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CLK
INPUT SIGNAL
CLK
OUTPUT SIGNAL
input data
Tissignal
output data
Tovsignal
Tihsignal
Tohsignal
Table 17-1 Format of timing parameter tables
Signal Clock Setup parameter Percent of clock period Hold parameter
INPUT CLK Tisinput 50% Tihinput
OUTPUT PCLK Tovoutput 30% Tohoutput