Cortex-A8 Technical Reference Manual - ARM Information Center

12.4.11 Instruction Transfer Register
Debug
31 3 2 1 0
Figure 12-9 Debug State Cache Control Register format
Table 12-19 shows how the bit values correspond with the Debug State Cache Control Register
functions.
Bits Field Function
[31:3] - Reserved. RAZ, SBZP.
Reserved
The ITR enables the external debugger to feed instructions into the core for execution while in
debug state. The ITR is a write-only register. Reads from the ITR return an Unpredictable value.
Figure 12-10 shows the bit arrangement of the ITR.
Not write-through
Reserved
Data and unified cache linefill
Table 12-19 Debug State Cache Control Register bit functions
[2] Not write-through Not write-through:
0 = force write-through behavior for regions marked as write-back in debug state, reset
value
1 = normal operation of regions marked as write-back in debug state.
[1] - Reserved. RAZ, SBZP.
[0] Data and unified
cache linefill
Data and unified cache linefill:
0 = L1 data cache and L2 cache linefills disabled in debug state, reset value
1 = normal operation of L1 data cache and L2 cache in debug state.
31 0
Figure 12-10 ITR format
Table 12-20 shows how the bit values correspond with the Instruction Transfer Register
functions.
Bits Field Function
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 12-25
ID060510 Non-Confidential
Data
Table 12-20 Instruction Transfer Register bit functions
[31:0] - Indicates an ARM instruction for the processor to execute while in debug state. The reset value is
Unpredictable.
Note
Writes to the ITR when the processor is not in debug state or the DSCR[13] execute instruction
enable bit is 0 are Unpredictable.