Cortex-A8 Technical Reference Manual - ARM Information Center

Conditional execution
Glossary
includes the Data Transfer Register, some bits of the Data Status and Control Register, and the
external debug interface controller, such as the DBGTAP controller in the case of the JTAG
interface.
If the condition code flags indicate that the corresponding condition is true when the instruction
starts executing, it executes normally. Otherwise, the instruction does nothing.
Content Addressable Memory (CAM)
Memory that is identified by its contents. Content Addressable Memory is used in CAM-RAM
architecture caches to store the tags for cache entries.
CAM includes comparison logic with each bit of storage. A data value is broadcast to all words
of storage and compared with the values there. Words that match are flagged in some way.
Subsequent operations can then work on flagged words. It is possible to read the flagged words
out one at a time or write to certain bit positions in all of them.
Context The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and
the associated memory access permissions.
See also Fast context switch.
Control bits The bottom eight bits of a Program Status Register. The control bits change when an exception
arises and can be altered by software only when the processor is in a privileged mode.
Coprocessor A processor that supplements the main processor. It carries out additional functions that the
main processor cannot perform. Usually used for floating-point math calculations, signal
processing, or memory management.
Copy back See Write-back.
Core A core is that part of a processor that contains the ALU, the datapath, the general-purpose
registers, the Program Counter, and the instruction decode and control circuitry.
Core reset See Warm reset.
CoreSight The infrastructure for monitoring, tracing, and debugging a complete system on chip.
CPSR See Current Program Status Register
Cross Trigger Interface (CTI)
Part of an Embedded Cross Trigger device. The CTI provides the interface between a core/ETM
and the CTM within an ECT.
Cross Trigger Matrix (CTM)
The CTM combines the trigger requests generated from CTIs and broadcasts them to all CTIs
as channel triggers within an Embedded Cross Trigger device.
CTI See Cross Trigger Interface.
CTM See Cross Trigger Matrix.
Current Program Status Register (CPSR)
The register that holds the current operating processor status.
Data Abort An indication from a memory system to the core of an attempt to access an illegal data memory
location. An exception must be taken if the processor attempts to use the data that caused the
abort.
See also Abort, External Abort, and Prefetch Abort.
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