Cortex-A8 Technical Reference Manual - ARM Information Center

Instruction L1
Data 0 register
Instruction L1
Data 1 register
3.2.80 c15, GHB array operations
To write one entry in the instruction side BTB array, for example:
System Control Coprocessor
31 28 27
0
Reserved
31 30 29 11 10
3 2 0
Address
Reserved
Figure 3-78 BTB array write operation format
LDR R0, =0x01234567;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R2, =0x0DDFFFFF;
MCR p15, 0, R2, c15, c1, 1; Move R0 to I-L1 Data 1 Register
LDR R1, =0x40000408;
MCR p15, 0, R1, c15, c5, 3; Write I-L1 Data 0 or 1 Register to BTB
To read one entry in instruction side BTB array, for example:
LDR R1, =0x40000408;
MCR p15, 0, R1, c15, c7, 3; Read BTB into I-L1 Data 0 or 1 Register
MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c1, 1; Move I-L1 Data 1 Register to R2
The purpose of the Global History Buffer (GHB) array operation is to:
• read the GHB array contents and write into the system debug data registers
• write into the system debug data registers and into the GHB array.
The GHB array operation is accessible in secure privileged modes only.
Figure 3-79 shows the bit arrangement of the GHB array read operation.
Figure 3-79 GHB array read operation format
Figure 3-80 on page 3-136 shows the bit arrangement of the GHB array write operation.
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ID060510 Non-Confidential
Data
Data
Reserved Address
31 10 9 2 1
0
Reserved Address
Address
Reserved
Address
Reserved
Write data
BTB
array
GHB
array