Cortex-A8 Technical Reference Manual - ARM Information Center

Figure 12-18 shows the bit arrangement of the PRSR.
Debug
31 3 2 1 0
Table 12-31 shows how the bit values correspond with the PRSR functions.
Bits Field Function
[31:4] - Reserved. RAZ, SBZP.
Reserved
Sticky reset status
Reset status
Sticky power-down status
Power-down status
Figure 12-18 PRSR format
Table 12-31 PRSR bit functions
[3] Sticky reset status Sticky reset status bit. This bit is cleared to 0 on read:
0 = the processor has not been reset since the last time this register was read
1 = the processor has been reset since the last time this register was read.
This sticky bit is set to 1 when either ARESETn or nPORESET is asserted.
This sticky bit is set to 0 when PRESETn is asserted.
If both PRESETn and ARESETn or nPORESET are asserted at the same time,
this bit is set to an Unpredictable value.
[2] Reset status Reset status bit:
0 = the processor is not currently held in reset
1 = the processor is currently held in reset.
This bit reads 1 when either ARESETn or nPORESET is asserted.
[1] Sticky power-down status Sticky power-down status bit. This bit is cleared to 0 on read:
0 = the processor has not powered down since the last time this register was read
1 = the processor has powered down since the last time this register was read. This
is the reset value.
[0] Power-down status Power-down status bit. This status bit reflects the invert value of the
DBGPWRDWNREQ input:
0 = the core is not powered up
1 = the core is powered up.
Note
On system reset, PRSR[1] resets to 1. Table 12-6 on page 12-10 specified that if PRSR[1] is set
to 1, then accessing any register in the core power domain results in an error response. For these
reasons, the debugger cannot access any register in the core power domain unless the debugger
clears PRSR[1] to 0.
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