Cortex-A8 Technical Reference Manual - ARM Information Center

Bits Field Access a Function
System Control Coprocessor
[13] V bit Banked Determines the location of exception vectors, see c12, Secure or Nonsecure Vector Base
Address Register on page 3-117. The primary input VINITHI defines the reset value of
the V bit:
0 = Normal exception vectors selected, reset value. The Vector Base Address Registers
determine the address range.
1 = High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.
[12] I bit Banked Determines if instructions can be cached in any instruction cache at any cache level:
0 = instruction caching disabled at all levels, reset value
1 = instruction caching enabled.
[11] Z bit Banked Enables program flow prediction:
0 = program flow prediction disabled, reset value
1 = program flow prediction enabled.
[10:7] - - Reserved. RAZ, SBZP.
[6:3] - - Reserved. Read-As-One (RAO), Should-Be-One or Preserved (SBOP).
[2] C bit Banked Determines if data can be cached in a data or unified cache at any cache level:
0 = data caching disabled at all levels, reset value
1 = data caching enabled.
[1] A bit Banked Enables strict alignment of data to detect alignment faults in data accesses:
0 = strict alignment fault checking disabled, reset value
1 = strict alignment fault checking enabled.
[0] M bit Banked Enables the MMU:
0 = MMU disabled, reset value
1 = MMU enabled.
a. The reset values for Secure and Non-secure banked access for the Control Register are the same.
Attempts to read or write the Control Register from secure or nonsecure User modes result in
an Undefined Instruction exception.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH
result in an Undefined Instruction exception, see Security Extensions write access disable on
page 2-35.
Table 3-47 shows the actions that result from attempted access for each mode.
To access the Control Register, read or write CP15 with:
MRC p15, 0, , c1, c0, 0 ; Read Control Register
Table 3-46 Control Register bit functions (continued)
Table 3-47 Results of access to the Control Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Secure
bit
Secure
bit
Nonsecure
bit
Nonsecure
bit
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
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