Cortex-A8 Technical Reference Manual - ARM Information Center

EN b
Table 3-96 shows the results of attempted access for each mode.
To access the EVTSEL Register, read or write CP15 with:
MRC p15, 0, , c9, c13, 1 ; Read EVTSEL Register
MCR p15, 0, , c9, c13, 1 ; Write EVTSEL Register
System Control Coprocessor
Table 3-96 Results of access to the Event Selection Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Data Data Undefined Undefined Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. The EN bit in c9, User Enable Register on page 3-89 enables User mode access of the Performance Monitor Registers.
Value Description
Table 3-97 shows the range values for predefined events that you can monitor using the
EVTSEL Register.
Table 3-97 Values for predefined events
0x00 Software increment. The register is incremented only on writes to the Software Increment Register. See c9,
Software Increment Register on page 3-81.
0x01 Instruction fetch that causes a refill at the lowest level of instruction or unified cache. Each instruction fetch
from normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that do
not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Where
instruction fetches consist of multiple instructions, these accesses count as single events. CP15 cache
maintenance operations do not count as events. This counter increments for speculative instruction fetches
and for fetches of instructions that reach execution.
0x02 Instruction fetch that causes a TLB refill at the lowest level of TLB. Each instruction fetch that causes a
translation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenance
operations do not count as events. This counter increments for speculative instruction fetches and for fetches
of instructions that reach execution.
0x03 Data read or write operation that causes a refill at the lowest level of data or unified cache. Each data read
from or write to normal cacheable memory that causes a refill from outside of the cache is counted. Accesses
that do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted.
Each access to a cache line to normal cacheable memory that causes a new linefill is counted, including the
multiple transaction of instructions such as LDM or STM, PUSH and POP. Write-through writes that hit in
the cache do not cause a linefill and so are not counted. CP15 cache maintenance operations do not count as
events. This counter increments for speculative data accesses and for data accesses that are explicitly made
by instructions.
0x04 Data read or write operation that causes a cache access at the lowest level of data or unified cache. Each
access to a cache line to normal cacheable memory is counted including the multiple transaction of
instructions such as LDM or STM. CP15 cache maintenance operations do not count as events. This counter
increments for speculative data accesses and for data accesses that are explicitly made by instructions.
0x05 Data read or write operation that causes a TLB refill at the lowest level of TLB. Each data read or write
operation that causes a translation table walk or an access to another level of TLB caching is counted. CP15
TLB maintenance operations do not count as events. This counter increments for speculative data accesses
and for data accesses that are explicitly made by instructions.
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