Cortex-A8 Technical Reference Manual - ARM Information Center

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3.2.52 c9, Interrupt Enable Set Register
Table 3-101 shows the results of attempted access for each mode.
To access the USEREN Register, read or write CP15 with:
MRC p15, 0, , c9, c14, 0 ; Read USEREN Register
MCR p15, 0, , c9, c14, 0 ; Write USEREN Register
System Control Coprocessor
Table 3-101 Results of access to the User Enable Register
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Data Data Data Data
Undefined
exception
1 Data Data Data Data Data Undefined
exception
The purpose of the INTerrupt ENable Set (INTENS) Register is to determine if any of the
Performance Monitor Count Registers, PMCNT0-PMCNT3 and CCNT, generate an interrupt
on overflow.
The INTENS Register is:
• a read/write register common to Secure and Nonsecure states
• accessible in privileged mode only.
When reading this register, any interrupt overflow enable bit that reads as 0 indicates the
interrupt overflow flag is disabled. Any interrupt overflow enable bit that reads as 1 indicates
the interrupt overflow flag is enabled.
When writing this register, any interrupt overflow enable bit written with a value of 0 is ignored,
that is, not updated. Any interrupt overflow enable bit written with a value of 1 sets the interrupt
overflow enable bit.
Figure 3-46 shows the bit arrangement of the INTENS Register.
C
Figure 3-46 Interrupt Enable Set Register format
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Data
Undefined
exception
Data Undefined
exception
31 30
4 3 2 1 0
Reserved
P3
P2
P1
P0