Cortex-A8 Technical Reference Manual - ARM Information Center

ORR , , #0x0020_0000; Set parity/ECC enable
MCR p15, 1, , c9, c0, 2 ; Write L2 Cache Auxiliary Control Register
MRC p15, 1, , c9, c0, 2 ; Read L2 Cache Auxiliary Control Register
TST , #0x0020_0000 ; Test for parity/ECC enable
BEQ no_parity_ram_setup
parity_ram_setup:
;
B done_parity_RAM_setup
no_parity_ram_setup:
;
done_parity_RAM_setup:
;
3.2.56 c10, TLB Lockdown Registers
System Control Coprocessor
The purpose of the TLB Lockdown Registers is to control the fully-associative TLB entries to
allocate on the next table walk. The TLB is normally allocated on a rotating basis. The oldest
entry is always the next allocated.
You can configure the TLB Lockdown Registers to exclude a range of entries from the
round-robin allocation scheme. You must use the TLB Lockdown Registers with the TLB
preload operation. See c10, TLB preload operation on page 3-99 for more information.
The TLB Lockdown Registers are:
• read/write registers common to Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-50 shows the bit arrangement of the Data and Instruction TLB Lockdown Registers.
Figure 3-50 TLB Lockdown Register format
Table 3-110 shows how the bit values correspond with the Data and Instruction TLB Lockdown
Register functions.
Bits Field Function
31 27 26 22 21 1 0
Base Victim Reserved P
Table 3-110 TLB Lockdown Register bit functions
[31:27] Base Defines the offset from TLB entry 0 for which entries 0 to base - 1 are locked assuming P equals 1
during a hardware translation table walk.
[26:22] Victim Specifies the entry where the next hardware translation table walk can place a TLB entry. The reset
value is 0. Each hardware translation table walk increments the value of the Victim field.
[21:1] - Reserved. UNP, SBZP.
[0] P Determines if TLB entries allocated by subsequent translation table walks are not invalidated by the
Invalidate TLB unlocked entries operation:
0 = allocated TLB entries are invalidated, reset value
1 = allocated TLB entries are not invalidated.
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