Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.38 c6, Data Fault Address Register
Table 3-70 shows the results of attempted access for each mode.
To access the Auxiliary Fault Status Registers, read or write CP15 with:
System Control Coprocessor
Table 3-70 Results of access to the Auxiliary Fault Status Registers a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Secure
data
Secure
data
Nonsecure
data
Nonsecure
data
MRC p15, 0, , c5, c1, 0; Read Data Auxiliary Fault Status Register
MCR p15, 0, , c5, c1, 0; Write Data Auxiliary Fault Status Register
MRC p15, 0, , c5, c1, 1; Read Instruction Auxiliary Fault Status Register
MCR p15, 0, , c5, c1, 1; Write Instruction Auxiliary Fault Status Register
There is no physical register for Auxiliary Data Fault Status Register or Auxiliary Instruction
Fault Status Register as the register is always RAZ.
The purpose of the Data Fault Address Register (DFAR) is to hold the Modified Virtual Address
(MVA) of the fault when a precise abort occurs.
The DFAR is:
• a read/write register banked for Secure and Nonsecure states
• accessible in privileged modes only.
The Data Fault Address Register bits [31:0] contain the MVA where the precise abort occurred.
Table 3-71 shows the results of attempted access for each mode.
To access the DFAR, read or write CP15 with:
MRC p15, 0, , c6, c0, 0 ; Read Data Fault Address Register
MCR p15, 0, , c6, c0, 0 ; Write Data Fault Address Register
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
Table 3-71 Results of access to the Data Fault Address Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Secure
data
Secure
data
Nonsecure
data
Nonsecure
data
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
A write to this register sets the DFAR to the value of the data written. This is useful for a
debugger to restore the value of the DFAR.
The processor also updates the DFAR on debug exception entry because of watchpoints. See
Effect of debug exceptions on CP15 registers and WFAR on page 12-54 for more information.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-67
ID060510 Non-Confidential