Cortex-A8 Technical Reference Manual - ARM Information Center

14.5.3 Enabling events
14.5.4 Address comparators
Embedded Trace Macrocell
The processor can perform two 32-bit data transfers in a cycle. The ETM treats a 64-bit data
transfer as two 32-bit data transfers. The ViewData enabling event is calculated once per cycle.
The other parts of ViewData are calculated once per data transfer.
If the processor performs two 32-bit data transfers in a cycle, the ETM can trace neither, one, or
both of them. ViewData is recalculated for each transfer. However, because the enabling event
is only calculated once per cycle, address comparators selected using the enabling event cause
both data transfers to be traced as if a match occurs on each transfer.
The TraceEnable and ViewData enabling events are Precise if only the following is selected:
• Precise single address comparators
• Precise address range comparators
• instrumentation resources
• context ID comparator
• nonsecure state resource
• prohibited resource
• hard-wired resource, always true.
The following events are delayed by two cycles compared to the timing of their input events,
and are Imprecise:
• counters at zero
• sequence state 1, 2, or 3
• trace start/stop resource.
The following events are Imprecise and have no fixed timing relationship with other events:
• external input
• extended external input selectors.
Single address comparators and address range comparators are always Precise if the exact match
bit for that comparator is cleared to 0. This includes cases where the address comparator is
conditional on the context ID comparator matching.
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