Cortex-A8 Technical Reference Manual - ARM Information Center

LEN Vector
length
13.4.3 Floating-point Exception Register, FPEXC
The FPEXC Register is accessible in privileged modes only.
NEON and VFP Programmers Model
b110 7 b11 2 Unpredictable Unpredictable
b111 8 b00 1 Work normally Unpredictable
b111 8 b11 2 Unpredictable Unpredictable
The EN bit, FPEXC[30], is the NEON and VFP enable bit. Clearing EN disables the NEON and
VFP coprocessor. The EN bit is cleared to 0 on reset.
Figure 13-5 shows the bit arrangement of the FPEXC Register.
EN
EX
Figure 13-5 Floating-Point Exception Register format
Table 13-10 shows how the bit values correspond with the FPEXC Register functions.
Bits Field Function
13.4.4 Media and VFP Feature Registers, MVFR0 and MVFR1
Table 13-9 Vector length and stride combinations (continued)
STRIDE Vector
stride
Single-precision
vector instructions
The Media and VFP Feature Registers, MVFR0 and MVFR1, describe the features supported
by the NEON and VFP coprocessor. These registers are accessible in privileged modes only.
Figure 13-6 shows the bit arrangement of the MVFR0 Register.
Double-precision
vector instructions
31 30 29 0
Reserved
Table 13-10 Floating-Point Exception Register bit functions
[31] EX Exception bit. This bit specifies how much information must be saved to record the state of the
Advanced SIMD and VFP system. See the ARM Architecture Reference Manual, ARMv7-A and
ARMv7-R edition.
[30] EN NEON and VFP enable bit. Setting the EN bit to 1 enables the NEON and VFP coprocessor. Reset
clears EN to 0.
[29:0] - Reserved.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
RM SV SR D TE DP SP
Figure 13-6 MVFR0 Register format
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