Cortex-A8 Technical Reference Manual - ARM Information Center

Powering up the NEON power domain while the processor is not in reset
Clock, Reset, and Power Control
To apply power to the NEON power domain while the processor is not in reset, use the sequence
that follows. With the NEON power domain currently powered down, it is assumed that
ARESETNEONn is asserted.
1. Software must disable access to the NEON unit using the Coprocessor Access Control
Register, see c1, Coprocessor Access Control Register on page 3-52.
MRC p15, 0, , c1, c0, 2; Read Coprocessor Access Control Register
BIC , , #0xF00000; Disable access to CP10 and CP11
MCR p15, 0, , c1, c0, 2; Write Coprocessor Access Control Register
2. Software must signal to the external system that it is safe to power up the NEON unit.
3. Apply power to the NEON power domain.
4. Deassert ARESETNEONn. NEON requires a minimum of 20 CLK cycles to complete
its reset sequence. Therefore, the system must wait until NEON has completed its reset
sequence before releasing the NEON clamps.
5. Release the NEON output clamps by deasserting CLAMPNEONOUT.
6. Software must poll the external system to determine that it is safe to enable the NEON
unit.
After the completion of the reset sequence, you can enable the NEON unit using the
Coprocessor Access Control Register. See c1, Coprocessor Access Control Register on
page 3-52.
Debug and ETM power domains
If the core is running in an environment where debug facilities are not required, you can reduce
leakage power by powering down the debug PCLK, ETM CLK, and ETM ATCLK power
domains. Debug PCLK, ETM CLK, and ETM ATCLK power domains must be built using a
common power supply.
Powering down the debug and ETM power domains
To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, the
implementation must place debug PCLK, ETM CLK, and ETM ATCLK on a separately
controlled and shared power supply. In addition, the outputs of debug PCLK, ETM CLK, and
ETM ATCLK must be clamped to benign values while powered down to indicate that the
interface is idle.
To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, apply the
following sequence:
1. Assert both PRESETn and ATRESETn. You must assert PRESETn for at least eight
PCLK cycles and ATRESETn for at least eight ATCLK cycles before asserting
CLAMPDBGOUT.
2. Activate the debug PCLK, ETM CLK, and ETM ATCLK output clamps by asserting the
CLAMPDBGOUT input HIGH.
3. Remove power from the debug PCLK, ETM CLK, and ETM ATCLK power domains.
PRESETn and ATRESETn must remain asserted while the domain is powered down.
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