Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.70 c12, Interrupt Status Register
System Control Coprocessor
Note
The Monitor Vector Base Address Register is 0x00000000 at reset. The secure boot code must
program the register with an appropriate value for the Monitor.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH
result in an Undefined Instruction exception, see Security Extensions write access disable on
page 3-5.
Table 3-139 shows the results of attempted access for each mode.
Table 3-139 Results of access to the Monitor Vector Base Address Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Data Undefined Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
To access the Monitor Vector Base Address Register, read or write CP15 with:
MRC p15, 0, , c12, c0, 1 ; Read Monitor Vector Base Address Register
MCR p15, 0, , c12, c0, 1 ; Write Monitor Vector Base Address Register
The purpose of the Interrupt Status Register is to:
• reflect the state of the nFIQ and nIRQ pins on the processor
• reflect the state of external aborts.
The Interrupt Status Register is:
• a read-only register common to Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-63 shows the bit arrangement of the Interrupt Status Register.
31 9 8 7 6 5 0
Reserved
A I F
Reserved
Figure 3-63 Interrupt Status Register format
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