Cortex-A8 Technical Reference Manual - ARM Information Center

EN b
3.2.44 c9, Count Enable Clear Register
Table 3-85 shows the results of attempted access for each mode.
To access the CNTENS Register, read or write CP15 with:
MRC p15, 0, , c9, c12, 1 ; Read CNTENS Register
MCR p15, 0, , c9, c12, 1 ; Write CNTENS Register
System Control Coprocessor
Table 3-84 Count Enable Set Register bit functions (continued)
The purpose of the CouNT ENable Clear (CNTENC) Register is to enable or disable any of the
Performance Monitor Count Registers.
When reading this register, any enable that reads as 0 indicates the counter is disabled. Any
enable that reads as 1 indicates the counter is enabled.
When writing this register, any enable written with a value of 0 is ignored, that is, not updated.
Any enable written with a value of 1 clears the counter enable to 0.
The CNTENC Register is:
• a read/write register common to Secure and Nonsecure states
• accessible as determined by c9, User Enable Register on page 3-89.
Figure 3-40 shows the bit arrangement of the CNTENC Register.
Bits Field Function
[2] P2 Enable Counter 2.
[1] P1 Enable Counter 1.
[0] P0 Enable Counter 0.
Table 3-85 Results of access to the Count Enable Set Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Data Data Undefined Undefined Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. The EN bit in c9, User Enable Register on page 3-89 enables User mode access of the Performance Monitor Registers.
31 30
4 3 2 1 0
C
Reserved
Figure 3-40 Count Enable Clear Register format
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P3
P2
P1
P0