Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.83 c15, L2 tag array operations
To read one entry from the L2 parity/ECC array, for example:
System Control Coprocessor
LDR R1, =0x400000C0 ;
MCR p15, 0, R1, c15, c9, 4; Read L2 parity/ECC RAM into L2 Data 0 Register
MRC p15, 0, R2, c15, c8, 0; Move L2 Data 0 Register to R2
The purpose of the L2 tag array operations is to:
• read the L2 tag array contents and write into the system debug data registers
• write into the system debug data registers and copy into the L2 tag array.
The L2 tag array operation is accessible in secure privileged modes only. You can determine the
value of N in Figure 3-86 and Figure 3-87 from Table 3-163 on page 3-139.
Figure 3-86 shows the bit arrangement of the L2 tag array read operation.
31 29 28
N+1 N
6 5 0
Address
Reserved Address Reserved
Figure 3-86 L2 tag array read operation format
Note
In Figure 3-86, bits [31:29] also correspond to the L2 cache way numbers.
Figure 3-87 shows the bit arrangement of the L2 tag array write operation.
L2 Data 0 register Tag
Reserved
Address
To write one entry to the L2 tag array, for example:
Figure 3-87 L2 tag array write operation format
LDR R0, =0x000020D1;
MCR p15, 0, R0, c15, c8, 0; Move R0 to L2 Data 0 Register
LDR R1, =0x400000C0;
MCR p15, 0, R1, c15, c8, 2; Write L2 Data 0 Register to L2 tag RAM
To read one entry from the L2 tag array, for example:
LDR R1, =0x400000C0;
MCR p15, 0, R1, c15, c9, 2; Read L2 tag RAM into L2 Data 0 Register
MRC p15, 0, R2, c15, c8, 0; Move L2 Data 0 Register to R2
Address
Reserved
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-140
ID060510 Non-Confidential
Tag
array
31 N+1 N 8 7 5 4 2 1 0
31 29 28
N+1 N
6 5 0
Reserved Address
Reserved
Data
Address
Write data
Data
Tag
array