Cortex-A8 Technical Reference Manual - ARM Information Center

11.2.3 Reset handling
11.2.4 Safe shift RAM signals
When either of these modes is asserted:
Design for Test
• if the TESTEGATE signal is LOW, the flops within the ETM unit cannot be updated
• if the TESTNGATE signal is LOW, the flops within the NEON unit cannot be updated
• the rest of the flops within the Cortex-A8 core are not updated when the TESTCGATE
signal is LOW.
If these signals are HIGH, then the flip-flops that they control are allowed to update. When both
MBISTMODE and TESTMODE are negated, the values of the TESTEGATE,
TESTNGATE, and TESTCGATE inputs are not used.
The internal asynchronous reset signals are driven from a flip-flop. SE prevents the resettable
registers from being corrupted during shift using the logic shown in Figure 11-29.
Reset pipeline
register
Figure 11-29 Reset handling
The Cortex-A8 core has separate safe shift RAM signal for each logical unit that uses it, they
are:
• SAFESHIFTRAMIF
• SAFESHIFTRAMLS
• SAFESHIFTRAML2.
These safe shift RAM signals are top-level signals with scan enable functionality. They are
asserted during scan shifting to gate off the chip selects and write enables of the L1 cache
RAMs. These signals are also used to gate off the clock signal to the L2 cache RAMs, as
Figure 11-30 shows.
Figure 11-30 Safe shift RAM signal
One methodology for testing the shadow logic of the RAMs is to test through the RAMs. The
ATPG tool uses this gate for easier testability of this logic for this methodology. However, if
there is a scan chain or bypass wrapper within the RAM, this gate prevents the clock from
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D Q
SE
safe shift RAM signal
Functional chip select/write enable
safe shift RAM signal
internal clock
To active-LOW asynchronous
reset ports of flip-flops
chip select/write enable
to L1 RAM
clock to L2 RAM