Cortex-A8 Technical Reference Manual - ARM Information Center

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List of Figures Figure 3-17 Silicon ID Register format ......................................................................................................... 3-41 Figure 3-18 Cache Size Identification Register format ................................................................................. 3-42 Figure 3-19 Cache Size Selection Register format ...................................................................................... 3-43 Figure 3-20 Control Register bit assignments .............................................................................................. 3-45 Figure 3-21 Auxiliary Control Register format .............................................................................................. 3-48 Figure 3-22 Coprocessor Access Control Register format ........................................................................... 3-52 Figure 3-23 Secure Configuration Register format ....................................................................................... 3-53 Figure 3-24 Secure Debug Enable Register format ..................................................................................... 3-55 Figure 3-25 Nonsecure Access Control Register format .............................................................................. 3-56 Figure 3-26 Translation Table Base Register 0 format ................................................................................ 3-58 Figure 3-27 Translation Table Base Register 1 format ................................................................................ 3-59 Figure 3-28 Translation Table Base Control Register format ....................................................................... 3-61 Figure 3-29 Domain Access Control Register format ................................................................................... 3-62 Figure 3-30 Data Fault Status Register format ............................................................................................. 3-63 Figure 3-31 Instruction Fault Status Register format .................................................................................... 3-65 Figure 3-32 c7 format for set and way .......................................................................................................... 3-70 Figure 3-33 c7 format for MVA ..................................................................................................................... 3-71 Figure 3-34 PA Register format for successful translation ........................................................................... 3-71 Figure 3-35 PA Register format for unsuccessful translation ....................................................................... 3-72 Figure 3-36 TLB Operations MVA and ASID format .................................................................................... 3-76 Figure 3-37 TLB Operations ASID format .................................................................................................... 3-76 Figure 3-38 Performance Monitor Control Register format .......................................................................... 3-77 Figure 3-39 Count Enable Set Register format ............................................................................................ 3-78 Figure 3-40 Count Enable Clear Register format ......................................................................................... 3-79 Figure 3-41 FLAG Register format ............................................................................................................... 3-81 Figure 3-42 Software Increment Register format ......................................................................................... 3-82 Figure 3-43 Performance Counter Selection Register format ...................................................................... 3-83 Figure 3-44 Event Selection Register format ............................................................................................... 3-84 Figure 3-45 User Enable Register format ..................................................................................................... 3-89 Figure 3-46 Interrupt Enable Set Register format ........................................................................................ 3-90 Figure 3-47 Interrupt Enable Clear Register format ..................................................................................... 3-92 Figure 3-48 L2 Cache Lockdown Register format ........................................................................................ 3-93 Figure 3-49 L2 Cache Auxiliary Control Register format .............................................................................. 3-95 Figure 3-50 TLB Lockdown Register format ................................................................................................. 3-98 Figure 3-51 Primary Region Remap Register format ................................................................................. 3-101 Figure 3-52 Normal Memory Remap Register format ................................................................................ 3-102 Figure 3-53 PLE Identification and Status Registers format ...................................................................... 3-105 Figure 3-54 PLE User Accessibility Register format .................................................................................. 3-106 Figure 3-55 PLE Channel Number Register format ................................................................................... 3-108 Figure 3-56 PLE Control Register format ................................................................................................... 3-110 Figure 3-57 PLE Internal Start Address Register bit format ....................................................................... 3-112 Figure 3-58 PLE Internal End Address Register format ............................................................................. 3-113 Figure 3-59 PLE Channel Status Register format ...................................................................................... 3-114 Figure 3-60 PLE Context ID Register format .............................................................................................. 3-116 Figure 3-61 Secure or Nonsecure Vector Base Address Register format .................................................. 3-117 Figure 3-62 Monitor Vector Base Address Register format ........................................................................ 3-118 Figure 3-63 Interrupt Status Register format .............................................................................................. 3-119 Figure 3-64 FCSE PID Register format ...................................................................................................... 3-121 Figure 3-65 Address mapping with the FCSE PID Register ....................................................................... 3-122 Figure 3-66 Context ID Register format ..................................................................................................... 3-122 Figure 3-67 Instruction and Data side Data 0 Registers format ................................................................. 3-125 Figure 3-68 Instruction and Data side Data 1 Registers format ................................................................. 3-125 Figure 3-69 L1 TLB CAM read operation format ........................................................................................ 3-129 Figure 3-70 L1 TLB CAM write operation format ........................................................................................ 3-129 Figure 3-71 L1 HVAB array read operation format ..................................................................................... 3-131 Figure 3-72 L1 HVAB array write operation format .................................................................................... 3-131 Figure 3-73 L1 tag array read operation format ......................................................................................... 3-132 Figure 3-74 L1 tag array write operation format ......................................................................................... 3-132 Figure 3-75 L1 data array read operation format ....................................................................................... 3-133 Figure 3-76 L1 data array write operation format ....................................................................................... 3-133 ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. xvi ID060510 Non-Confidential
List of Figures Figure 3-77 BTB array read operation format ............................................................................................ 3-134 Figure 3-78 BTB array write operation format ............................................................................................ 3-135 Figure 3-79 GHB array read operation format ............................................................................................ 3-135 Figure 3-80 GHB array write operation format ........................................................................................... 3-136 Figure 3-81 L2 Data 0 Register format ....................................................................................................... 3-137 Figure 3-82 L2 Data 1 Register format ....................................................................................................... 3-137 Figure 3-83 L2 Data 2 Register format ....................................................................................................... 3-137 Figure 3-84 L2 parity/ECC array read operation format ............................................................................. 3-139 Figure 3-85 L2 parity/ECC array write operation format ............................................................................. 3-139 Figure 3-86 L2 tag array read operation format ......................................................................................... 3-140 Figure 3-87 L2 tag array write operation format ......................................................................................... 3-140 Figure 3-88 L2 data RAM array read operation format .............................................................................. 3-141 Figure 3-89 L2 data RAM array write operation format .............................................................................. 3-141 Figure 6-1 16MB supersection descriptor format ......................................................................................... 6-4 Figure 8-1 L2 cache bank structure .............................................................................................................. 8-3 Figure 10-1 CLK-to-ACLK ratio of 4:1 .......................................................................................................... 10-2 Figure 10-2 Changing the CLK-to-ACLK ratio from 4:1 to 1:1 ...................................................................... 10-3 Figure 10-3 Changing the PCLK-to-internal-PCLK ratio from 4:1 to 1:1 ...................................................... 10-3 Figure 10-4 Changing the ATCLK-to-internal-ATCLK ratio from 4:1 to 1:1 .................................................. 10-3 Figure 10-5 Power-on reset timing ............................................................................................................... 10-5 Figure 10-6 Soft reset timing ........................................................................................................................ 10-6 Figure 10-7 PRESETn and ATRESETn assertion ....................................................................................... 10-6 Figure 10-8 STANDBYWFI deassertion ....................................................................................................... 10-9 Figure 10-9 CLKSTOPREQ and CLKSTOPACK ......................................................................................... 10-9 Figure 10-10 Power domains ....................................................................................................................... 10-12 Figure 10-11 Voltage domains ..................................................................................................................... 10-14 Figure 10-12 Retention power domains ....................................................................................................... 10-21 Figure 11-1 L1 MBIST Instruction Register bit assignments ........................................................................ 11-3 Figure 11-2 L2 MBIST Instruction Register bit assignments ........................................................................ 11-6 Figure 11-3 L1 and L2 MBIST GO-NOGO Instruction Registers bit assignments ..................................... 11-10 Figure 11-4 L1 MBIST GO-NOGO Instruction Register example with two patterns ................................... 11-11 Figure 11-5 L1 MBIST Datalog Register bit assignments .......................................................................... 11-11 Figure 11-6 L2 MBIST Datalog Register bit assignments .......................................................................... 11-12 Figure 11-7 Timing of MBIST instruction load ............................................................................................ 11-15 Figure 11-8 Timing of MBIST custom GO-NOGO instruction load ............................................................. 11-16 Figure 11-9 Timing of MBIST at-speed execution ...................................................................................... 11-16 Figure 11-10 Timing of MBIST end-of-test datalog retrieval ........................................................................ 11-17 Figure 11-11 Timing of MBIST start of bitmap datalog retrieval ................................................................... 11-17 Figure 11-12 Timing of MBIST end of bitmap datalog retrieval .................................................................... 11-18 Figure 11-13 Physical array after pass 1 of CKBD ....................................................................................... 11-20 Figure 11-14 Physical array after pass 1 of COLBAR .................................................................................. 11-21 Figure 11-15 Physical array after pass 1 of ROWBAR ................................................................................ 11-21 Figure 11-16 Row 1 column 2 state during pass 2 of RWXMARCH ............................................................ 11-22 Figure 11-17 Row 1 column 2 state during pass 2 of RWYMARCH ............................................................ 11-22 Figure 11-18 Row 1 column 2 state during pass 2 of RWRXMARCH .......................................................... 11-23 Figure 11-19 Row 1 column 2 state during pass 2 of RWRYMARCH .......................................................... 11-23 Figure 11-20 Row 1 column 2 state during pass 2 of XMARCHC ................................................................ 11-24 Figure 11-21 Row 1 column 2 state during pass 2 of YMARCHC ................................................................ 11-24 Figure 11-22 XADDRBAR array accessing and data ................................................................................... 11-25 Figure 11-23 YADDRBAR array accessing and data ................................................................................... 11-25 Figure 11-24 WRITEBANG .......................................................................................................................... 11-26 Figure 11-25 READBANG ............................................................................................................................ 11-26 Figure 11-26 Input wrapper boundary register cell control logic .................................................................. 11-28 Figure 11-27 Output wrapper boundary register cell control logic ................................................................ 11-29 Figure 11-28 IEEE 1500-compliant input wrapper boundary register cell .................................................... 11-29 Figure 11-29 Reset handling ........................................................................................................................ 11-30 Figure 11-30 Safe shift RAM signal .............................................................................................................. 11-30 Figure 12-1 Typical debug system ............................................................................................................... 12-2 Figure 12-2 Debug ID Register format ....................................................................................................... 12-13 Figure 12-3 Debug ROM Address Register format .................................................................................... 12-14 ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. xvii ID060510 Non-Confidential
Page 1 and 2: Copyright © 2006-2010 ARM Limited.
Page 3 and 4: Web Address http://www.arm.com ARM
Page 5 and 6: Contents 2.14 The program status re
Page 7 and 8: Contents 16.6 Instruction-specific
Page 9 and 10: List of Tables Table 3-16 Debug Fea
Page 11 and 12: List of Tables Table 3-136 Secure o
Page 13 and 14: List of Tables Table 12-59 Values t
Page 15: List of Figures Cortex-A8 Technical
Page 19 and 20: List of Figures Figure 15-16 CTI Ch
Page 21 and 22: About this manual Product revision
Page 23 and 24: old Highlights interface elements,
Page 25 and 26: Feedback Feedback on the product Fe
Page 27 and 28: 1.1 About the processor Introductio
Page 29 and 30: 1.3 Components of the processor L1
Page 31 and 32: 1.3.6 NEON 1.3.7 ETM The NEON unit
Page 33 and 34: 1.5 Debug Introduction The processo
Page 35 and 36: 1.7 Configurable options Table 1-1
Page 37 and 38: Introduction • The various data a
Page 39 and 40: 1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
Page 41 and 42: Chapter 2 Programmers Model This ch
Page 43 and 44: 2.2 Thumb-2 instruction set Program
Page 45 and 46: Bits Field Function Programmers Mod
Page 47 and 48: 2.4 Jazelle Extension 2.4.1 Jazelle
Page 49 and 50: 2.5 Security Extensions architectur
Page 51 and 52: 2.6 Advanced SIMD architecture Prog
Page 53 and 54: 2.8 Processor operating states 2.8.
Page 55 and 56: 2.10 Memory formats 2.10.1 Byte-inv
Page 57 and 58: 2.12 Operating modes Programmers Mo
Page 59 and 60: System and User r0 r1 r2 r3 r4 r5 r
Page 61 and 62: 2.14 The program status registers 2
Page 63 and 64: 2.14.5 The GE[3:0] bits Programmers
Page 65 and 66: Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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Page 181 and 182:
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
Page 387 and 388:
12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
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15.6.4 CTI Application Trigger Clea
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Table 15-10 shows how the bit value
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15.6.12 ASIC Control Register, ASIC
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15.7 CTI Integration Test Registers
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15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
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Cross Trigger Interface Table 15-26
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15.8.3 Device Type Identifier, 0xFC
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Cross Trigger Interface Table 15-31
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16.1 About instruction cycle timing
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Instruction Cycle Timing Example 16
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Table 16-4 shows the operation of m
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Table 16-9 shows the operation of l
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d. See Load/store instructions on p
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Instruction Cycle Timing Table 16-1
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16.4 Other pipeline-dependent laten
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16.4.5 Conditional instructions Ins
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16.6 Instruction-specific schedulin
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Instruction Cycle Timing VNEG Dd,Dm
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VMLA a VMLS a VMLAa VMLSa VQDMLAa V
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VSLI VSRI 16.6.5 Advanced SIMD floa
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16.6.6 Advanced SIMD byte permute i
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Instruction Table 16-23 shows the o
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Instruction VST3 3-reg (unaligned)
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Instruction VLD3 3-reg (unaligned)
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Instruction Single precision cycles
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• FMACS, FNMACS • FMSCS, FNMSCS
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is dual issued with previous instru
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17.1 About setup and hold times AC
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17.2 AXI interface Table 17-2 shows
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17.3 ATB and CTI interfaces Table 1
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AC Characteristics Table 17-4 Timin
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17.6 L2 preload interface AC Charac
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17.8 Miscellaneous signals AC Chara
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A.1 AXI interface Signal Descriptio
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A.3 MBIST and DFT interface A.3.1 M
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A.4 Preload engine interface Table
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A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
Page 565 and 566:
Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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