Cortex-A8 Technical Reference Manual - ARM Information Center

Figure 3-38 shows the bit arrangement of the PMNC Register.
IMP
System Control Coprocessor
31 24 23 16 15 11 10 6 5 4 3 2 1 0
IDCODE N
Reserved
Figure 3-38 Performance Monitor Control Register format
Table 3-82 shows how the bit values correspond with the PMNC Register functions.
Bits Field Function
[31:24] IMP Specifies the implementor code:
0x41 = ARM.
[23:16] IDCODE Specifies the identification code:
0x0.
[15:11] N Specifies the number of counters implemented:
0x4 = 4 counters implemented.
[10:6] - Reserved. RAZ, SBZP.
D C P E
Table 3-82 Performance Monitor Control Register bit functions
[5] DP Disables cycle counter, CCNT, when non-invasive debug is prohibited:
0 = count is enabled in regions where non-invasive debug is prohibited
1 = count is disabled in regions where non-invasive debug is prohibited.
[4] X Enables export of the events from the event bus to an external monitoring block, such as the ETM
to trace events:
0 = export disabled, reset value
1 = export enabled.
[3] D Cycle count divider:
0 = counts every processor clock cycle, reset value
1 = counts every 64th processor clock cycle.
[2] C Cycle counter reset:
0 = no action
1 = resets cycle counter, CCNT, to zero.
This bit Read-As-Zero.
[1] P Performance counter reset:
0 = no action
1 = resets all performance counters to zero.
This bit Read-As-Zero.
[0] E Enable bit:
0 = disables all counters, including CCNT
1 = enables all counters including CCNT.
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DP
X