Cortex-A8 Technical Reference Manual - ARM Information Center

Table 12-5 shows the APB interface access permissions with relation to software lock.
Power down permission
Debug
Table 12-5 APB interface access with relation to software lock
Conditions Registers
PADDR31 Lock LAR Other registers
Access to registers inside the core power domain is not possible when the core powers down.
The APB interface ignores accesses to powered-down registers and returns an error response,
that is, PSLVERR is set to 1.
When the core powers down, the PRSR[1] sticky power down bit is set to 1. While PRSR[1] is
set to 1, the APB interface also ignores accesses to registers inside the core power domain and
returns an error response, that is, PSLVERR is set to 1. This bit remains set until the debugger
reads the PRSR. See Device Power Down and Reset Status Register on page 12-36 for more
details.
Table 12-6 shows the behavior of APB interface accesses to debug registers with relation to
power-down event.
Conditions Registers
DBGPWRDWNREQ
Sticky power
down
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 12-10
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1 a
X b
0 1 d
OK c
OK
OK WI e
0 0 OK OK
a. The PADDR31 signal is HIGH, indicating the
external debugger generated the access.
b. X indicates a Don’t care condition. The
outcome does not depend on this condition.
c. OK indicates that the access succeeds.
d. LSR[1] bit is set to 1.
e. WI indicates that writes are ignored, and that
reads do not change the processor state.
Table 12-6 Debug registers access with relation to power-down event
OS Lock DIDR, ECR, DRCR Other debug a Management b
1 X c X OK d ERR e OK
0 f 0 0 OK OK OK
0 0 1 g OK ERR OK
0 1 h X OK ERR OK
a. This column indicates registers in the address range of 0x000 through 0xF00 except for DIDR, ECR, DRCR, and the power
management registers specified in Table 12-7 on page 12-11.
b. This column indicates registers in the address range of 0xF04 through 0xFFC.
c. X indicates a Don’t care condition. The outcome does not depend on this condition.
d. OK indicates that the access succeeds.
e. ERR indicates a PSLVERR error response; written value is ignored and reads return an Unpredictable value.
f. The DBGPWRDWNREQ signal is LOW, indicating the processor is powered up.
g. 1 indicates that OSLSR[1] is set to 1.
h. 1 indicates that PRSR[1] is set to 1.