Cortex-A8 Technical Reference Manual - ARM Information Center

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2.14.10 Reserved bits Bits in Figure 2-12 on page 2-21 that are in this category are J and T. Programmers Model • Bits that can only be modified from privileged modes, and that are completely protected from modification by instructions while the processor is in User mode. The only way that these bits can be modified while the processor is in User mode is by entering a processor exception, as described in Exceptions on page 2-27. Bits in Figure 2-12 on page 2-21 that are in this category are: — A — I — F — M[4:0]. Only secure privileged modes can write directly to the CPSR mode bits to enter Monitor mode. If the core is in secure User mode, nonsecure User mode, or nonsecure privileged modes it ignores changes to the CPSR to enter the Secure Monitor. The core does not copy mode bits in the SPSR that are changed in the Nonsecure state, across to the CPSR. The remaining bits in the PSRs are unused and reserved. When changing a PSR flag or control bits, make sure that you do not alter these reserved bits. You must ensure that your program does not rely on reserved bits containing specific values because future processors might use some or all of the reserved bits. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 2-26 ID060510 Non-Confidential
2.15 Exceptions 2.15.1 Exception entry and exit summary Exception or entry Programmers Model Exceptions occur whenever the processor temporarily halts the normal flow of a program, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the processor preserves the current processor state so the original program can resume when the handler routine finishes. If two or more exceptions occur simultaneously, the processor deals with exceptions in the fixed order given in Exception priorities on page 2-33. This section provides details of the processor exception handling: • Exception entry and exit summary • Leaving an exception on page 2-28. • Reset on page 2-28 • Fast interrupt request on page 2-28 • Interrupt request on page 2-29 • Aborts on page 2-29 • Imprecise data abort mask in the CPSR/SPSR on page 2-31 • Software interrupt instruction on page 2-31 • Software Monitor Instruction on page 2-31 • Undefined instruction on page 2-32 • Breakpoint instruction on page 2-32 • Exception vectors on page 2-32 • Exception priorities on page 2-33 Table 2-12 summarizes the PC value preserved in the relevant r14 on exception entry and the recommended instruction for exiting the exception handler. Table 2-12 Exception entry and exit Return instruction Previous state Notes ARM r14_x Thumb r14_x SVC MOVS PC, R14_svc PC + 4 PC+2 Where the PC is the address of the SVC, SMC, or Undefined instruction SMC MOVS PC, R14_mon PC + 4 - UNDEF MOVS PC, R14_und PC + 4 PC+2 PABT SUBS PC, R14_abt, #4 PC + 4 PC+4 Where the PC is the address of instruction that had the prefetch abort FIQ SUBS PC, R14_fiq, #4 PC + 4 PC+4 Where the PC is the address of the instruction that was not executed because IRQ SUBS PC, R14_irq, #4 PC + 4 PC+4 the FIQ or IRQ took priority DABT SUBS PC, R14_abt, #8 PC + 8 PC+8 Where the PC is the address of the load or store instruction that generated the data abort RESET - - - The value saved in r14_svc on reset is Unpredictable BKPT SUBS PC, R14_abt, #4 PC + 4 PC+4 Software breakpoint ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 2-27 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
Page 15 and 16: List of Figures Cortex-A8 Technical
Page 17 and 18: List of Figures Figure 3-77 BTB arr
Page 19 and 20: List of Figures Figure 15-16 CTI Ch
Page 21 and 22: About this manual Product revision
Page 23 and 24: old Highlights interface elements,
Page 25 and 26: Feedback Feedback on the product Fe
Page 27 and 28: 1.1 About the processor Introductio
Page 29 and 30: 1.3 Components of the processor L1
Page 31 and 32: 1.3.6 NEON 1.3.7 ETM The NEON unit
Page 33 and 34: 1.5 Debug Introduction The processo
Page 35 and 36: 1.7 Configurable options Table 1-1
Page 37 and 38: Introduction • The various data a
Page 39 and 40: 1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
Page 41 and 42: Chapter 2 Programmers Model This ch
Page 43 and 44: 2.2 Thumb-2 instruction set Program
Page 45 and 46: Bits Field Function Programmers Mod
Page 47 and 48: 2.4 Jazelle Extension 2.4.1 Jazelle
Page 49 and 50: 2.5 Security Extensions architectur
Page 51 and 52: 2.6 Advanced SIMD architecture Prog
Page 53 and 54: 2.8 Processor operating states 2.8.
Page 55 and 56: 2.10 Memory formats 2.10.1 Byte-inv
Page 57 and 58: 2.12 Operating modes Programmers Mo
Page 59 and 60: System and User r0 r1 r2 r3 r4 r5 r
Page 61 and 62: 2.14 The program status registers 2
Page 63 and 64: 2.14.5 The GE[3:0] bits Programmers
Page 65: Mode bits Programmers Model M[4:0]
Page 69 and 70: 2.15.5 Interrupt request 2.15.6 Abo
Page 71 and 72: This restores both the PC and the C
Page 73 and 74: 2.15.13 Exception priorities Progra
Page 75 and 76: 2.17 Hardware consideration for Sec
Page 77 and 78: SECMONOUT[78] instruction caches at
Page 79 and 80: Chapter 3 System Control Coprocesso
Page 81 and 82: System Control Coprocessor Register
Page 83 and 84: 3.1.3 MMU control and configuration
Page 85 and 86: 3.2 System control coprocessor regi
Page 87 and 88: CRn Op1 CRm Op2 Register or operati
Page 97 and 98: 3.2.2 c0, Main ID Register System C
Page 99 and 100: 3.2.4 c0, TCM Type Register 3.2.5 c
Page 101 and 102: 3.2.7 c0, Processor Feature Registe
Page 103 and 104: • accessible in privileged modes
Page 105 and 106: System Control Coprocessor Table 3-
Page 107 and 108: Bits Field Function [11:8] L1 Harva
Page 109 and 110: Bits Field Function [11:8] Harvard
Page 111 and 112: 31 28 27 24 23 20 19 16 15 12 11 8
Page 113 and 114: Table 3-30 shows the results of att
Page 115 and 116: System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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System Control Coprocessor Table 3-
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
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15.6.4 CTI Application Trigger Clea
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Table 15-10 shows how the bit value
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15.6.12 ASIC Control Register, ASIC
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15.7 CTI Integration Test Registers
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15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
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Cross Trigger Interface Table 15-26
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15.8.3 Device Type Identifier, 0xFC
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Cross Trigger Interface Table 15-31
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16.1 About instruction cycle timing
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Instruction Cycle Timing Example 16
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Table 16-4 shows the operation of m
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Table 16-9 shows the operation of l
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d. See Load/store instructions on p
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Instruction Cycle Timing Table 16-1
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16.4 Other pipeline-dependent laten
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16.4.5 Conditional instructions Ins
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16.6 Instruction-specific schedulin
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Instruction Cycle Timing VNEG Dd,Dm
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VMLA a VMLS a VMLAa VMLSa VQDMLAa V
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VSLI VSRI 16.6.5 Advanced SIMD floa
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16.6.6 Advanced SIMD byte permute i
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Instruction Table 16-23 shows the o
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Instruction VST3 3-reg (unaligned)
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Instruction VLD3 3-reg (unaligned)
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Instruction Single precision cycles
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• FMACS, FNMACS • FMSCS, FNMSCS
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is dual issued with previous instru
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17.1 About setup and hold times AC
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17.2 AXI interface Table 17-2 shows
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17.3 ATB and CTI interfaces Table 1
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AC Characteristics Table 17-4 Timin
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17.6 L2 preload interface AC Charac
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17.8 Miscellaneous signals AC Chara
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A.1 AXI interface Signal Descriptio
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A.3 MBIST and DFT interface A.3.1 M
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A.4 Preload engine interface Table
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A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
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Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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