Cortex-A8 Technical Reference Manual - ARM Information Center

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Chapter 10 Clock, Reset, and Power Control This chapter describes the clock domains and reset inputs of the processor. It also describes dynamic and static power control techniques. It contains the following sections: • Clock domains on page 10-2 • Reset domains on page 10-4 • Power control on page 10-8. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 10-1 ID060510 Non-Confidential
10.1 Clock domains 10.1.1 AXI clocking using ACLKEN Clock, Reset, and Power Control The processor has three major clock domains: CLK High speed core clock used to clock all major processor interfaces. The Cortex-A8 processor uses only the rising edge of CLK. CLK controls the following units within the processor: • instruction fetch unit • instruction decode unit • instruction execute unit • load/store unit • L2 cache unit, including AXI interface • NEON unit • ETM unit, not including the ATB interface • debug logic, not including the APB interface. Note The instruction fetch, instruction decode, instruction execute, load/store, and L2 cache are called the core or integer core. PCLK APB clock that controls the debug interface for the processor. PCLK is asynchronous to CLK and ATCLK. PCLK controls the debug interface and logic in the PCLK domain. ATCLK ATB clock that controls the ATB interface for the processor. ATCLK is asynchronous to CLK and PCLK. ATCLK controls the ATB interface. Note You can implement PCLK and ATCLK to be synchronous to CLK. You can also implement PCLK and ATCLK to run synchronously to each other. The processor contains a single synchronous AXI interface. The AXI interface is clocked using a gated CLK that is gated using ACLKEN. The AXI interface can operate at any integer multiple slower than the processor clock, CLK. In previous ARM family of processors, sampling ACLKEN on the rising edge of CLK indicated that the rising edge of the AXI bus clock, ACLK, had occurred. However, for the processor, the cycle timing of ACLKEN has changed. Figure 10-1 shows the timing behavior of ACLKEN. CLK ACLKEN ACLK 2 cycles Figure 10-1 CLK-to-ACLK ratio of 4:1 Note Figure 10-1 shows the timing relationship between the AXI bus clock, ACLK, and ACLKEN, where ACLKEN asserts two CLK cycles prior to the rising edge of ACLK. It is critical that the relationship between ACLK and ACLKEN is maintained. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 10-2 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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Page 231 and 232: 5.4 Guidelines for optimal performa
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Page 235 and 236: 6.1 About the MMU Memory Management
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Page 243 and 244: 7.1 About the L1 memory system Leve
Page 245 and 246: 7.2.6 Instruction cache maintenance
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Page 257 and 258: 8.3 Enabling and disabling the L2 c
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Page 265 and 266: 8.7 Parity and error correction cod
Page 267 and 268: 9.1 About the external memory inter
Page 269 and 270: Integer data and CP14 writes Noncac
Page 271 and 272: 9.4 AXI data read/write transaction
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Page 275 and 276: Noncacheable store word Noncacheabl
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Page 295 and 296: Powering up the debug and ETM domai
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Page 301 and 302: Chapter 11 Design for Test This cha
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Page 309 and 310: Design for Test Not all row setting
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Page 317 and 318: End-of-test datalog retrieval Desig
Page 319 and 320: Pattern N RWRXMARCH 8N Row-fast Sta
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
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15.6.4 CTI Application Trigger Clea
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Table 15-10 shows how the bit value
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15.6.12 ASIC Control Register, ASIC
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15.7 CTI Integration Test Registers
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15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
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Cross Trigger Interface Table 15-26
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15.8.3 Device Type Identifier, 0xFC
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Cross Trigger Interface Table 15-31
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16.1 About instruction cycle timing
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Instruction Cycle Timing Example 16
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Table 16-4 shows the operation of m
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Table 16-9 shows the operation of l
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d. See Load/store instructions on p
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Instruction Cycle Timing Table 16-1
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16.4 Other pipeline-dependent laten
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16.4.5 Conditional instructions Ins
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16.6 Instruction-specific schedulin
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Instruction Cycle Timing VNEG Dd,Dm
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VMLA a VMLS a VMLAa VMLSa VQDMLAa V
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VSLI VSRI 16.6.5 Advanced SIMD floa
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16.6.6 Advanced SIMD byte permute i
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Instruction Table 16-23 shows the o
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Instruction VST3 3-reg (unaligned)
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Instruction VLD3 3-reg (unaligned)
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Instruction Single precision cycles
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• FMACS, FNMACS • FMSCS, FNMSCS
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is dual issued with previous instru
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17.1 About setup and hold times AC
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17.2 AXI interface Table 17-2 shows
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17.3 ATB and CTI interfaces Table 1
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AC Characteristics Table 17-4 Timin
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17.6 L2 preload interface AC Charac
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17.8 Miscellaneous signals AC Chara
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A.1 AXI interface Signal Descriptio
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A.3 MBIST and DFT interface A.3.1 M
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A.4 Preload engine interface Table
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A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
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Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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