Cortex-A8 Technical Reference Manual - ARM Information Center

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11.1 MBIST 11.1.1 About MBIST 11.1.2 MBIST registers This section describes the array architecture and operation of the MBIST: • About MBIST • MBIST registers • MBIST operation on page 11-14 • Pattern selection on page 11-18. The processor has three separate MBIST controllers: Design for Test L1 and L2 MBIST controllers The L1 and L2 MBIST controllers communicate with RAM arrays distributed around the chip. Their controls are directly ported to the interface for use with external testbench or Automated Test Equipment (ATE) drivers. CAMBIST controller The CAMBIST controller is a slave of the L1 MBIST controller. It targets the comparator logic of the Content-Addressable Memory (CAM). The L1 MBIST controller tests the contents of the I-CAM and D-CAM arrays. The following arrays require MBIST support: • Instruction cache (I-cache) • Data cache (D-cache) • Global History Buffer (GHB) • Branch Target Buffer (BTB) • Translation Look-aside Buffer (TLB) Note The TLB has separate instruction and data arrays, each containing an attribute array, a CAM array, and a Physical Address (PA) array. • Hash Virtual Address Buffer (HVAB) • L1 tag RAM • all L2 cache RAM such as data, parity, tag, and valid RAMs. Table 11-1 shows the MBIST registers. See Figure 11-7 on page 11-15 for information about the timing of an MBIST instruction load. Register Access Reference Table 11-1 MBIST register summary L1 MBIST Instruction Register W See L1 MBIST Instruction Register on page 11-3 L2 MBIST Instruction Register W See L2 MBIST Instruction Register on page 11-6 L1 and L2 MBIST GO-NOGO Instruction Registers W See L1 and L2 MBIST GO-NOGO Instruction Registers on page 11-10 L1 MBIST Datalog Register R See L1 MBIST Datalog Register on page 11-11 L2 MBIST Datalog Register R See L2 MBIST Datalog Register on page 11-12 ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 11-2 ID060510 Non-Confidential
In L1 MBIST Instruction Register Figure 11-1 shows the fields of the L1 MBIST Instruction Register. pttn[5:0] L1_array_sel[22:0] rtfail bitmap dseed[3:0] pttn[5:0] Design for Test Figure 11-1 L1 MBIST Instruction Register bit assignments Use the pttn[5:0] field to select test patterns as Table 11-2 shows. Note The PTTN_SLAVE pattern (b111111) is for testing only the I-CAMBIST and D-CAMBIST. rtfail HVAB_rows[2:0] GHB_rows[2:0] BTB_rows[2:0] TAG_rows[2:0] DATA_rows[2:0] Field Selected test pattern pttn[5:0] Pattern select field: a L1_config[14:0] b010010 = PTTN_WRITE_SOLID b010011 = PTTN_READ_SOLID b100001 = PTTN_SOLIDS b000010 = PTTN_WRITE_CKBD b000011 = PTTN_READ_CKBD b100011 = PTTN_CKBD b000100 = PTTN_XMARCH_C b000101 = PTTN_PTTN_FAIL b000110 = PTTN_RW_XMARCH b000111 = PTTN_RW_YMARCH b001000 = PTTN_RWR_XMARCH b001001 = PTTN_RWR_YMARCH b001010 = PTTN_WRITEBANG a. See Pattern selection on page 11-18. b. Default value of pttn[5:0]. L1_ADDR_SCRAMBLE[183:0] Table 11-2 Selecting a test pattern with pttn[5:0] b101010 = PTTN_READBANG b001011 = PTTN_YMARCH_C b001100 = PTTN_WRITE_ROWBAR b001101 = PTTN_READ_ROWBAR b101101 = PTTN_ROWBAR b001110 = PTTN_WRITE_COLBAR b001111 = PTTN_READ_COLBAR b101111 = PTTN_COLBAR b010000 = PTTN_RW_XADDRBAR b010001 = PTTN_RW_YADDRBAR b010100 = PTTN_ADDR_DEC b000000 = PTTN_GONOGOb b111111 = PTTN_SLAVE Setting the rtfail bit to 1 enables the fail signal to assert on every cycle that a failure occurs. Clearing the rtfail bit to 0 causes a sticky failure reporting, and the fail signal remains asserted after the first failure that occurs. Reset clears the rtfail bit to 0. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 11-3 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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Page 265 and 266: 8.7 Parity and error correction cod
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Page 277 and 278: LA Last Access External Memory Inte
Page 279 and 280: 10.1 Clock domains 10.1.1 AXI clock
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Page 295 and 296: Powering up the debug and ETM domai
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Page 301: Chapter 11 Design for Test This cha
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Page 309 and 310: Design for Test Not all row setting
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Page 313 and 314: Design for Test When testing the ta
Page 315 and 316: CLK ARESETn MBISTMODE MBISTSHIFT MB
Page 317 and 318: End-of-test datalog retrieval Desig
Page 319 and 320: Pattern N RWRXMARCH 8N Row-fast Sta
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Page 329 and 330: processor input ports WEXTEST WINTE
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Page 337 and 338: Instruction Mnemonic Description 12
Page 339 and 340: 12.3.6 Power domains and debug 12.3
Page 341 and 342: Table 12-5 shows the APB interface
Page 343 and 344: 12.4 Debug register descriptions Te
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Page 349 and 350: Bits Field Function [21:20] DTR acc
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
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15.6.4 CTI Application Trigger Clea
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Table 15-10 shows how the bit value
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15.6.12 ASIC Control Register, ASIC
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15.7 CTI Integration Test Registers
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15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
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Cross Trigger Interface Table 15-26
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15.8.3 Device Type Identifier, 0xFC
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Cross Trigger Interface Table 15-31
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16.1 About instruction cycle timing
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Instruction Cycle Timing Example 16
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Table 16-4 shows the operation of m
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Table 16-9 shows the operation of l
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d. See Load/store instructions on p
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Instruction Cycle Timing Table 16-1
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16.4 Other pipeline-dependent laten
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16.4.5 Conditional instructions Ins
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16.6 Instruction-specific schedulin
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Instruction Cycle Timing VNEG Dd,Dm
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VMLA a VMLS a VMLAa VMLSa VQDMLAa V
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VSLI VSRI 16.6.5 Advanced SIMD floa
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16.6.6 Advanced SIMD byte permute i
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Instruction Table 16-23 shows the o
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Instruction VST3 3-reg (unaligned)
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Instruction VLD3 3-reg (unaligned)
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Instruction Single precision cycles
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• FMACS, FNMACS • FMSCS, FNMSCS
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is dual issued with previous instru
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17.1 About setup and hold times AC
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17.2 AXI interface Table 17-2 shows
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17.3 ATB and CTI interfaces Table 1
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AC Characteristics Table 17-4 Timin
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17.6 L2 preload interface AC Charac
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17.8 Miscellaneous signals AC Chara
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A.1 AXI interface Signal Descriptio
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A.3 MBIST and DFT interface A.3.1 M
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A.4 Preload engine interface Table
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A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
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Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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