Cortex-A8 Technical Reference Manual - ARM Information Center

Debug
Table 12-17 shows the bit field definitions of the Vector Catch Register. In this table, VBAR is
the CP15 Vector Base Address Register for secure, VBARNS is CP15 Vector Base Address
Register for nonsecure, and MVBAR is CP15 Monitor Vector Base Address Register.
Bits Access Normal address
High vectors
address
Table 12-17 Vector Catch Register bit functions
Function
[31] RW VBARNS+0x0000001C 0xFFFF001C Vector catch enable, FIQ in Nonsecure state. The
reset value is 0.
[30] RW VBARNS+0x00000018 0xFFFF0018 Vector catch enable, IRQ in Nonsecure state. The
reset value is 0.
[29] R - - Reserved. RAZ, SBZP.
[28] RW VBARNS+0x00000010 0xFFFF0010 Vector catch enable, Data Abort in Nonsecure state.
The reset value is 0.
[27] RW VBARNS+0x0000000C 0xFFFF000C Vector catch enable, Prefetch Abort in Nonsecure
state. The reset value is 0.
[26] RW VBARNS+0x00000008 0xFFFF0008 Vector catch enable, SVC in Nonsecure state. The
reset value is 0.
[25] RW VBARNS+0x00000004 0xFFFF0004 Vector catch enable, Undefined instruction in
Nonsecure state. The reset value is 0.
[24:16] R - - Reserved. RAZ, SBZP.
[15] RW MVBAR+0x0000001C MVBAR+0x0000001C Vector catch enable, FIQ in Secure state. The reset
value is 0.
[14] RW MVBAR+0x00000018 MVBAR+0x00000018 Vector catch enable, IRQ in Secure state. The reset
value is 0.
[13] R - - Reserved. RAZ, SBZP.
[12] RW MVBAR+0x00000010 MVBAR+0x00000010 Vector catch enable, Data Abort in Secure state.
The reset value is 0.
[11] RW MVBAR+0x0000000C MVBAR+0x0000000C Vector catch enable, Prefetch Abort in Secure state.
The reset value is 0.
[10] RW MVBAR+0x00000008 MVBAR+0x00000008 Vector catch enable, SMC in Secure state. The reset
value is 0.
[9:8] R - - Reserved. RAZ, SBZP.
[7] RW VBAR+0x0000001C 0xFFFF001C Vector catch enable, FIQ in Secure state. The reset
value is 0.
[6] RW VBAR+0x00000018 0xFFFF0018 Vector catch enable, IRQ in Secure state. The reset
value is 0.
[5] R - - Reserved. RAZ, SBZP.
[4] RW VBAR+0x00000010 0xFFFF0010 Vector catch enable, Data Abort in Secure state.
The reset value is 0.
[3] RW VBAR+0x0000000C 0xFFFF000C Vector catch enable, Prefetch Abort in Secure state.
The reset value is 0.
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