Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.3 c0, Cache Type Register
MRC p15, 0, , c0, c0, 0 ; Read Main ID Register
System Control Coprocessor
See c0, Processor Feature Register 0 on page 3-23 - c0, Instruction Set Attributes Registers 5-7
on page 3-39 for more information on the processor features.
The purpose of the Cache Type Register is to determine the instruction and data cache minimum
line length in bytes to enable a range of addresses to be invalidated.
The Cache Type Register is:
• a read-only register
• accessible in privileged modes only.
The contents of the Cache Type Register depend on the specific implementation. Figure 3-2
shows the bit arrangement of the Cache Type Register.
31 28 27 24 23 20 19 16 15 14 13 4 3 0
1
0 0 0 0 0 0 0 DMinLine 0 0 0 0 0 0 0 0 0 0
Cache writeback granule
L1 Ipolicy
Figure 3-2 Cache Type Register format
Table 3-6 shows how the bit values correspond with the Cache Type Register functions.
Bits Field Function
[31:28] - Always read as 4'b1000.
Table 3-7 shows the results of attempted access for each mode.
IMinLine
Table 3-6 Cache Type Register bit functions
[27:24] Cache writeback granule Cache writeback granule. Log2 of the number of words of the maximum size of
memory that can be overwritten as a result of the eviction of a cache entry that has
had a memory location within it modified.
4'b0010 = cache writeback granule size is 4 words.
[23:20] - Always read as 4'b0000.
[19:16] DMinLine Number of words of smallest line length in L1 or L2 data cache:
4'b0100 = sixteen 32-bit word data line length.
[15:14] L1 Ipolicy VIPT instruction cache support:
2'b10 = virtual index, physical tag L1 Ipolicy.
[13: 4] - Always read as b0000000000.
[3:0] IMinLine Number of words of smallest line length in L1 or L2 instruction cache:
4'b0100 = sixteen 32-bit word data line length.
Table 3-7 Results of access to the Cache Type Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
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