Cortex-A8 Technical Reference Manual - ARM Information Center

itmap
Design for Test
Setting the bitmap bit to1 enables bitmap test mode. Reset clears the instruction register bitmap
bit to 0. See Bitmap test mode on page 11-15.
dseed[3:0]
Write the data seed in the dseed field. The MBIST controller repeats the dseed data to the full
array bus width. The reset value of dseed[3:0] is b0000.
L1_array_sel[22:0]
Set bits in the L1_array_sel[22:0] field to select the L1 arrays for test. The MBIST executes the
selected arrays serially beginning with the array indicated by the LSB. Table 11-3 shows how
each bit selects one of the L1 arrays. The reset value of the L1_array_sel is 23'h1FFFFF.
Table 11-3 Selecting the L1 arrays to test with L1_array_sel[22:0]
Bit Array selected
[0] I-RAM word0 [31:0] parity and dirty included. a
[1] I-RAM word1 [63:32] parity and dirty included. a
[2] I-RAM word2 [95:64] parity and dirty included. a
[3] I-RAM word3 [127:96] parity and dirty included. a
[4] I-CAM array.
[5] I-PA.
[6] I-tag.
[7] I-attributes of TLB.
[8] I-HVAB.
[9] BTBI. a
[10] BTBH. a
[11] GHB.
[12] D-RAM word0 [31:0] parity and dirty included. a
[13] D-RAM word1 [63:32] parity and dirty included. a
[14] D-RAM word2 [95:64] parity and dirty included. a
[15] D-RAM word3 [127:96] parity and dirty included. a
[16] D-CAM array.
[17] D-PA.
[18] D-tag.
[19] D-attributes of TLB.
[20] D-HVAB.
[21] I-CAMBIST. Tests CAM compare logic.
[22] D-CAMBIST. Tests CAM compare logic.
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