Cortex-A8 Technical Reference Manual - ARM Information Center

A.6 Miscellaneous signals
Table A-7 shows the signals not included in the previous tables.
Signal I/O Reset Description
nPORESET I - Active-LOW power-on reset input:
0 = apply power-on reset
1 = do not apply power-on reset.
ARESETn I - Active-LOW AXI reset input:
0 = apply AXI reset
1 = do not apply AXI reset.
ARESETNEONn I - Active-LOW NEON reset input:
0 = apply NEON reset
1 = do not apply NEON reset.
Signal Descriptions
Table A-7 Miscellaneous signals
SECMONOUTEN I - Security monitor output enable:
0 = disables SECMONOUT[86:0]
1 = enables SECMONOUT[86:0].
This pin is only sampled during reset of the processor.
L1RSTDISABLE I - L1 hardware reset disable input:
0 = the L1 valid RAM contents are reset by hardware
1 = the L1 valid RAM contents are not reset by hardware.
L2RSTDISABLE I - L2 hardware reset disable input:
0 = the L2 valid RAM contents are reset by hardware
1 = the L2 valid RAM contents are not reset by hardware.
CLKSTOPREQ I - Clock stop request:
0 = do not stop the internal clocks
1 = cause the processor to stop the internal clocks and to assert the
CLKSTOPACK output.
CLKSTOPACK O 0 Clock stop acknowledge:
0 = the internal clocks are not stopped
1 = the internal clocks are stopped.
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