Cortex-A8 Technical Reference Manual - ARM Information Center

CL bit
value
Table 3-107 shows the results of attempted access for each mode.
To access the L2 Cache Lockdown Register, read or write CP15 with:
MRC p15, 1, , c9, c0, 0 ; Read L2 Cache Lockdown Register
MCR p15, 1, , c9, c0, 0 ; Write L2 Cache Lockdown Register
Specific loading of addresses into cache way
System Control Coprocessor
The following procedure for lock down into a data or an instruction cache way i, with N cache
ways, using Format C, ensures that only the target cache way i is locked down.
This is the architecturally-defined method for locking data into caches:
1. Disable interrupts to ensure that no processor exceptions can occur during the execution
of this procedure. If this is not possible, all code and data that any exception handlers can
call must meet the conditions specified in step 2 and step 3.
2. Ensure that all data that the following code uses, apart from the data that is to be locked
down, is either:
• in a noncacheable area of memory
• in an already locked cache way.
3. Ensure that the data to be locked down is in a cacheable area of memory.
4. Ensure that the data to be locked down is not already in the cache, using either:
• cache clean
• invalidate
• cache clean and invalidate.
See c7, Cache operations on page 3-68.
5. Enable allocation to the target cache way by writing to the Instruction or Data Cache
Lockdown Register, with the CRm field set to 0, setting L to 0 for bit i, and L to 1 for all
other ways.
6. Ensure that the memory cache line is loaded into the cache by using an LDR instruction
to load a word from the memory cache line, for each of the cache lines to be locked down
in cache way i.
7. Write to the Instruction or Data Cache Lockdown Register, setting L to 1 for bit i and
restore all the other bits to the previous values before this routine was started.
Cache unlock procedure
Table 3-107 Results of access to the L2 Cache Lockdown Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
To unlock the lock down portion of the cache, write to register c9, setting L to 0 for each bit.
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