Cortex-A8 Technical Reference Manual - ARM Information Center

12.5.12 Identification Registers
Debug
31 8 7 4 3 0
Figure 12-28 Device Type Register format
Table 12-43 shows how the bit values correspond with the Device Type Register functions.
Bits Field Function
[31:8] - RAZ.
Reserved
Sub type Main class
Table 12-43 Device Type Register bit functions
[7:4] Sub type Indicates that the sub-type of the processor is core. This value is 0x1.
[3:0] Main class Indicates that the main class of the processor is debug logic. This value is 0x5.
The Identification Registers are read-only registers that consist of the Peripheral Identification
Registers and the Component Identification Registers. The Peripheral Identification Registers
provide standard information required by all CoreSight components. Only bits [7:0] of each
register are used, the remaining bits Read-As-Zero.
The Component Identification Registers identify the processor as a CoreSight component. Only
bits [7:0] of each register are used, the remaining bits Read-As-Zero. The values in these
registers are fixed.
Table 12-44 shows the offset value, register number, and description that are associated with
each Peripheral Identification Register.
Table 12-44 Peripheral Identification Registers
Offset Register number Function
0xFD0 1012 Peripheral Identification Register 4
0xFD4 1013 Reserved
0xFD8 1014 Reserved
0xFDC 1015 Reserved
0xFE0 1016 Peripheral Identification Register 0
0xFE4 1017 Peripheral Identification Register 1
0xFE8 1018 Peripheral Identification Register 2
0xFEC 1019 Peripheral Identification Register 3
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