Cortex-A8 Technical Reference Manual - ARM Information Center

• accessible in privileged modes only.
Figure 3-17 shows the bit arrangement of the Silicon ID Register.
System Control Coprocessor
Figure 3-17 Silicon ID Register format
Table 3-39 shows how the bit values correspond with the Silicon ID Register functions.
Table 3-40 shows the results of attempted access for each mode.
To access the Silicon ID Register, read CP15 with:
3.2.23 c0, Cache Size Identification Registers
31 24 23 16 15 8 7 4 3 0
Implementor
Bits Field Function
Feature Reserved
MRC p15, 1, , c0, c0, 7 ; Read Silicon ID Register
The purpose of these registers is to provide cache size information for up to eight levels of cache
containing instruction, data, or unified caches. The processor contains L1 and L2 cache. The
Cache Size Selection Register determines the Cache Size Identification Register to select.
The Cache Size Identification Registers are:
• read-only registers common for Secure and Nonsecure states
• accessible in privileged modes only.
Major
revision
Minor
revision
Table 3-39 Silicon ID Register bit functions
[31:24] Implementor This field contains a code that identifies the silicon manufacturer. ARM assigns this code.
[23:16] Feature This field is implementation-defined.
[15:8] - Reserved, RAZ.
[7:4] Major revision This field is implementation-defined.
[3:0] Minor revision This field is implementation-defined.
Table 3-40 Results of access to the Silicon ID Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
Figure 3-18 on page 3-42 shows the bit arrangement of the Cache Size Identification Register.
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