Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.72 c13, Context ID Register
System Control Coprocessor
Addresses issued by the processor in the range 0-32MB are translated by the ProcID. Address
A becomes A + (ProcID x 32MB). The MMU uses this translated address, the MVA. Addresses
above 32MB are not translated. The ProcID is a 7-bit field, enabling 128 x 32MB processes to
be mapped.
Note
If ProcID is 0, as it is on Reset, then there is a flat mapping between the processor and the MMU.
Figure 3-65 shows how addresses are mapped using the FCSE PID Register.
Virtual address (VA)
issued by the processor
4GB
32MB
Figure 3-65 Address mapping with the FCSE PID Register
The purpose of the Context ID Register is to provide information on the current ASID and
process ID, for example for the ETM and debug logic.
Debug logic uses the ASID information to enable process-dependent breakpoints and
watchpoints. The ASID field of the Context ID Register and FCSE PID Register cannot be used
simultaneously. The FCSE PID Register remapping of VA to MVA has priority over setting the
ASID field to designate non-global pages. Therefore, non-global pages cannot be used if the
FCSE PID Register is set to a non-zero value.
The Context ID Register is:
• a read/write register banked for Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-66 shows the bit arrangement of the Context ID Register.
Figure 3-66 Context ID Register format
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-122
ID060510 Non-Confidential
0
C13
Modified virtual address (MVA)
input to MMU
127
2
1
0
64MB
32MB
31 8 7 0
PROCID
ASID
4GB
0