Cortex-A8 Technical Reference Manual - ARM Information Center

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3.2.54 c9, L2 Cache Lockdown Register
System Control Coprocessor
31 30
4 3 2 1 0
C
Reserved
Figure 3-47 Interrupt Enable Clear Register format
Table 3-104 shows how the bit values correspond with the INTENC Register functions.
Table 3-105 shows the results of attempted access for each mode.
To access the INTENC Register, read or write CP15 with:
MRC p15, 0, , c9, c14, 2 ; Read INTENC Register
MCR p15, 0, , c9, c14, 2 ; Write INTENC Register
The L2 Cache Lockdown Register controls the L2 cache lockdown. The Lockdown Format C
provides a method to restrict the replacement algorithm on cache linefills to only use selected
cache ways within a set. Using this method, you can fetch or load code into the L2 cache and
protect data from being evicted, or you can use the method to reduce cache pollution.
The L2 Cache Lockdown Register is:
• a read-only or read/write register, depending on the security selected for the register
access using CL bit [16] in the c1, Nonsecure Access Control Register on page 3-56.
• accessible in privileged modes only.
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P3
P2
P1
P0
Table 3-104 Interrupt Enable Clear Register bit functions
Bits Field Function
[31] C CCNT overflow interrupt enable.
[30:4] - Reserved. UNP, SBZP.
[3] P3 PMCNT3 overflow interrupt enable.
[2] P2 PMCNT2 overflow interrupt enable.
[1] P1 PMCNT1 overflow interrupt enable.
[0] P0 PMCNT0 overflow interrupt enable.
Table 3-105 Results of access to the Interrupt Enable Clear Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Data Data Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.