RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
Bit 13 FBES: Fatal bus error status
This bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the
corresponding DMA engine disables all its bus accesses.
Bits 12:11 Reserved, must be kept at reset value.
Bit 10 ETS: Early transmit status
This bit indicates that the frame to be transmitted was fully transferred to the Transmit FIFO.
Bit 9 RWTS: Receive watchdog timeout status
This bit is asserted when a frame with a length greater than 2 048 bytes is received.
Bit 8 RPSS: Receive process stopped status
This bit is asserted when the receive process enters the Stopped state.
Bit 7 RBUS: Receive buffer unavailable status
This bit indicates that the next descriptor in the receive list is owned by the host and cannot
be acquired by the DMA. Receive process is suspended. To resume processing receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, receive process resumes when the
next recognized incoming frame is received. ETH_DMASR [7] is set only when the previous
receive descriptor was owned by the DMA.
Bit 6 RS: Receive status
This bit indicates the completion of the frame reception. Specific frame status information
has been posted in the descriptor. Reception remains in the Running state.
Bit 5 TUS: Transmit underflow status
This bit indicates that the transmit buffer had an underflow during frame transmission.
Transmission is suspended and an underflow error TDES0[1] is set.
Bit 4 ROS: Receive overflow status
This bit indicates that the receive buffer had an overflow during frame reception. If the partial
frame is transferred to the application, the overflow status is set in RDES0[11].
Bit 3 TJTS: Transmit jabber timeout status
This bit indicates that the transmit jabber timer expired, meaning that the transmitter had
been excessively active. The transmission process is aborted and placed in the Stopped
state. This causes the transmit jabber timeout TDES0[14] flag to be asserted.
Bit 2 TBUS: Transmit buffer unavailable status
This bit indicates that the next descriptor in the transmit list is owned by the host and cannot
be acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit
process state transitions. To resume processing transmit descriptors, the host should change
the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.
Bit 1 TPSS: Transmit process stopped status
This bit is set when the transmission is stopped.
Bit 0 TS: Transmit status
This bit indicates that frame transmission is finished and TDES1[31] is set in the first
descriptor.
Ethernet DMA operation mode register (ETH_DMAOMR)
Address offset: 0x1018
Reset value: 0x0000 0000
1005/1416 Doc ID 018909 Rev 3